uhd - Ettus' UHD Repository

	Commit message (Collapse)	Author	Age	Files	Lines
*	fpga: x400: cpld: Add manufacturing support	Humberto Jimenez	2021-12-01	4	-7/+27
\| \| \| \| \|	This commit enables a special personality on the X410 motherboard CPLD required for NI manufacturing purposes only.
*	fpga: x400: Refactor CPLDs build process	Humberto Jimenez	2021-12-01	33	-254/+733
\| \| \| \| \| \| \| \| \| \|	This commit refactors the X410's CPLDs build process to make it similar to other FPGA targets within the repo. The new process relies on basic Quartus build utilities. Additionally, this commit adds support for an alternative MAX10 CPLD for the motherboard CPLD implementation. Both previous (10M04) and new variant (10M08) are supported concurrently. The images package mapping is updated to reflect these changes.
*	x410: correct 100GbE link speed	Andrew Lynch	2021-11-02	2	-2/+2
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*	fpga: Remove stale references to UHD_FPGA_DIR	Wade Fife	2021-09-08	1	-2/+1
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*	fpga: Set default part for sim in setupenv.sh	Wade Fife	2021-08-30	1	-0/+4
\| \| \| \| \| \| \| \| \|	This sets the ARCH and PART_ID environment variables so that the selected part family is used for simulations by default. This can be overridden by changing them in the Makefile for the testbench if a testbench requires a specific part family. Prior to this change, the default was always ARCH=kintex7, PART_ID=xc7k410t/ffg900/-2, which required support for that part to be installed.
*	fpga: x400: Remove stale information in register map	Humberto Jimenez	2021-07-28	3	-9/+9
\| \| \| \| \| \|	White Rabbit is not supported in X410, however the register map included an incorrect reference to this unsupported feature. This commit removes the WR reference from both the source and html files.
*	fpga: x400: Fix x4xx_qsfp_wrapper testbench	Wade Fife	2021-06-22	1	-0/+3
\| \| \| \| \|	Reorder dependencies so that sc_util_v1_0_vl_rfs.sv gets compiled first when using ModelSim.
*	x400: sim: Move testbenches to sim folder	Wade Fife	2021-06-17	13	-0/+0
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*	fpga: Update testbenches to work in ModelSim	Wade Fife	2021-06-17	3	-76/+89
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*	fpga: x400: Add makefiles for RF testbenches	Wade Fife	2021-06-17	6	-0/+209
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*	fpga: x400: zbx: Add support for ZBX CPLD	Javier Valenzuela	2021-06-10	37	-0/+17727
\| \| \| \| \| \| \|	Co-authored-by: Cherwa Vang <cherwa.vang@ni.com> Co-authored-by: Martin Braun <martin.braun@ettus.com> Co-authored-by: Max Köhler <max.koehler@ni.com> Co-authored-by: Paul Butler <paul.butler@ni.com>
*	fpga: x400: cpld: Add support for X410 motherboard CPLD	Max Köhler	2021-06-10	42	-0/+8377
\| \| \| \| \|	Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com> Co-authored-by: Javier Valenzuela <javier.valenzuela@ni.com>
*	fpga: x400: Add support for X410 motherboard FPGA	Wade Fife	2021-06-10	204	-0/+299632
	Co-authored-by: Andrew Moch <Andrew.Moch@ni.com> Co-authored-by: Daniel Jepson <daniel.jepson@ni.com> Co-authored-by: Javier Valenzuela <javier.valenzuela@ni.com> Co-authored-by: Joerg Hofrichter <joerg.hofrichter@ni.com> Co-authored-by: Kumaran Subramoniam <kumaran.subramoniam@ni.com> Co-authored-by: Max Köhler <max.koehler@ni.com> Co-authored-by: Michael Auchter <michael.auchter@ni.com> Co-authored-by: Paul Butler <paul.butler@ni.com> Co-authored-by: Wade Fife <wade.fife@ettus.com> Co-authored-by: Hector Rubio <hrubio@ni.com>