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* fpga: Fix first arg in calls to $fatal()Wade Fife2022-07-201-15/+15
| | | | | | This fixes warnings regarding the first argument to $fatal(), which is supposed to be a number indicating what diagnostics to display. 1 corresponds to "Prints simulation time and location".
* fpga: x400: Fix AXI/LBUS testbench namesWade Fife2022-07-202-2/+2
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* fpga: rfnoc: Remove rfnoc_version from target YAMLWade Fife2022-06-104-4/+0
| | | | | | This causes the latest RFNoC protocol version to be used by default and avoids the need to update YAML files every time the RFNoC protocol version gets bumped.
* fpga: x400: Increase replay SEP buffer sizesWade Fife2022-04-066-28/+28
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* fpga: x400: Add timed commands support for all radio ctrlport endpointsJavier Valenzuela2022-04-047-182/+104
| | | | | | | | | | | | | Extends timed command support to all endpoints addressable by the radio ctrlport interface. Previously supported endpoints: - Daughterboard GPIO interface - RFDC timing control Newly supported endpoints: - DIO ATR control - DIO SPI control - DIO Source control
* fpga: Update all RFNoC imagesWade Fife2022-03-318-44/+44
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* rfnoc: Update device port names in image core YAMLWade Fife2022-03-314-174/+188
| | | | | | Update USRP RFNoC iamge core YAML files to use the more consistent device port names. Clean up the formatting and make the files more consistent.
* fpga: x400: Add x410_400_128_rfnoc_image_coreWade Fife2022-03-145-3/+1613
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* fpga: x400: Cleanup FPGA MakefileWade Fife2022-03-041-40/+61
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* fpga: x400: Add support for DRAM with 400 MHz BWWade Fife2022-03-042-22/+24
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* fpga: x400: Change AXI XB for DRAM to 512-bitWade Fife2022-03-041-106/+17
| | | | | | Change the width of the crossbar in the AXI Interconnect IP from 256-bit to 512-bit to match the DRAM memory controller width and to give better performance.
* fpga: x400: Add SPI Controller Info registerJavier Valenzuela2022-03-046-11/+156
| | | | | | Include a register that contains SPI controller information. Currently, it only provides the number of slaves addressable by the SPI engine.
* fpga: x400: Adjust SPI engine strobes alignmentJavier Valenzuela2022-03-044-9/+14
| | | | | | Modify behavior of clock crossing between radio_clk and radio_clk_2x. This ensures strobe signals are always asserted for a single radio_clk_2x cycle and when radio_clk is low.
* fpga: x400: Set replay SEP buffers to twice MTUWade Fife2022-02-242-8/+8
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* fpga: x400: Add DRAM enable macroJavier Valenzuela2022-02-101-0/+4
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* fpga: x400: zbx: cpld: Bump ZBX regmap copyrightJavier Valenzuela2022-02-1011-11/+11
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* fpga: x400: cpld: Bump CMI wrapper copyrightJavier Valenzuela2022-02-102-2/+2
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* fpga: x400: Bump minor versionWade Fife2022-02-073-8/+8
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* fpga: x400: Update rfnoc_image_core filesWade Fife2022-02-078-98/+1327
| | | | | Updates the RFNoC image core files to include DRAM and default image changes.
* fpga: x400: Add Replay to 100 and 200 MHz imagesWade Fife2022-02-072-36/+107
| | | | | This adds the RFNoC replay block to the defautl 100 and 200 MHz images for X410.
* fpga: x400: Add DRAM supportWade Fife2022-02-075-106/+1272
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* fpga: x400: Set DRAM speed to 2.0 GT/sWade Fife2022-02-071-26/+26
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* fpga: x400: Add axi_inter_4x64_512_bd IPWade Fife2022-02-073-0/+604
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* fpga: x400: Add axi_inter_2x128_512_bd IPWade Fife2022-02-073-0/+449
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* fpga: x400: cpld: Bump copyrightJavier Valenzuela2022-01-259-9/+9
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* fpga: x400: Bump copyrightJavier Valenzuela2022-01-2514-14/+14
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* fpga: x400: Expand PS GPIO port for DIO controlJavier Valenzuela2022-01-257-19/+58
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* fpga: x400: Add SPI bus support for GPIO portsJavier Valenzuela2022-01-259-60/+1338
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* fpga: x400: Add GPIO control via ATR and DB stateJavier Valenzuela2022-01-2514-199/+2932
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* fpga: x400: Connect Radio Blocks to DIOJavier Valenzuela2022-01-2510-305/+626
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* fpga: x400: Fix rfnoc_image_core.vh pathWade Fife2022-01-121-1/+1
| | | | | | Previously, when running rfnoc_image_builder, the rfnoc_image_core.vh file in the main x400 directory was being used instead of the one generated by rfnoc_image_builder.
* fpga: x400: cpld: Add manufacturing supportHumberto Jimenez2021-12-014-7/+27
| | | | | This commit enables a special personality on the X410 motherboard CPLD required for NI manufacturing purposes only.
* fpga: x400: Refactor CPLDs build processHumberto Jimenez2021-12-0133-254/+733
| | | | | | | | | | This commit refactors the X410's CPLDs build process to make it similar to other FPGA targets within the repo. The new process relies on basic Quartus build utilities. Additionally, this commit adds support for an alternative MAX10 CPLD for the motherboard CPLD implementation. Both previous (10M04) and new variant (10M08) are supported concurrently. The images package mapping is updated to reflect these changes.
* x410: correct 100GbE link speedAndrew Lynch2021-11-022-2/+2
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* fpga: Remove stale references to UHD_FPGA_DIRWade Fife2021-09-081-2/+1
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* fpga: Set default part for sim in setupenv.shWade Fife2021-08-301-0/+4
| | | | | | | | | This sets the ARCH and PART_ID environment variables so that the selected part family is used for simulations by default. This can be overridden by changing them in the Makefile for the testbench if a testbench requires a specific part family. Prior to this change, the default was always ARCH=kintex7, PART_ID=xc7k410t/ffg900/-2, which required support for that part to be installed.
* fpga: x400: Remove stale information in register mapHumberto Jimenez2021-07-283-9/+9
| | | | | | White Rabbit is not supported in X410, however the register map included an incorrect reference to this unsupported feature. This commit removes the WR reference from both the source and html files.
* fpga: x400: Fix x4xx_qsfp_wrapper testbenchWade Fife2021-06-221-0/+3
| | | | | Reorder dependencies so that sc_util_v1_0_vl_rfs.sv gets compiled first when using ModelSim.
* x400: sim: Move testbenches to sim folderWade Fife2021-06-1713-0/+0
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* fpga: Update testbenches to work in ModelSimWade Fife2021-06-173-76/+89
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* fpga: x400: Add makefiles for RF testbenchesWade Fife2021-06-176-0/+209
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* fpga: x400: zbx: Add support for ZBX CPLDJavier Valenzuela2021-06-1037-0/+17727
| | | | | | | Co-authored-by: Cherwa Vang <cherwa.vang@ni.com> Co-authored-by: Martin Braun <martin.braun@ettus.com> Co-authored-by: Max Köhler <max.koehler@ni.com> Co-authored-by: Paul Butler <paul.butler@ni.com>
* fpga: x400: cpld: Add support for X410 motherboard CPLDMax Köhler2021-06-1042-0/+8377
| | | | | Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com> Co-authored-by: Javier Valenzuela <javier.valenzuela@ni.com>
* fpga: x400: Add support for X410 motherboard FPGAWade Fife2021-06-10204-0/+299632
Co-authored-by: Andrew Moch <Andrew.Moch@ni.com> Co-authored-by: Daniel Jepson <daniel.jepson@ni.com> Co-authored-by: Javier Valenzuela <javier.valenzuela@ni.com> Co-authored-by: Joerg Hofrichter <joerg.hofrichter@ni.com> Co-authored-by: Kumaran Subramoniam <kumaran.subramoniam@ni.com> Co-authored-by: Max Köhler <max.koehler@ni.com> Co-authored-by: Michael Auchter <michael.auchter@ni.com> Co-authored-by: Paul Butler <paul.butler@ni.com> Co-authored-by: Wade Fife <wade.fife@ettus.com> Co-authored-by: Hector Rubio <hrubio@ni.com>
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