uhd - Ettus' UHD Repository

	Commit message (Collapse)	Author	Age	Files	Lines
*	fpga: Fix first arg in calls to $fatal()	Wade Fife	2022-07-20	1	-15/+15
\| \| \| \| \| \|	This fixes warnings regarding the first argument to $fatal(), which is supposed to be a number indicating what diagnostics to display. 1 corresponds to "Prints simulation time and location".
*	fpga: x400: Fix AXI/LBUS testbench names	Wade Fife	2022-07-20	2	-2/+2
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*	fpga: x400: Change AXI XB for DRAM to 512-bit	Wade Fife	2022-03-04	1	-106/+17
\| \| \| \| \| \|	Change the width of the crossbar in the AXI Interconnect IP from 256-bit to 512-bit to match the DRAM memory controller width and to give better performance.
*	fpga: x400: Set DRAM speed to 2.0 GT/s	Wade Fife	2022-02-07	1	-26/+26
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*	fpga: x400: Add axi_inter_4x64_512_bd IP	Wade Fife	2022-02-07	3	-0/+604
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*	fpga: x400: Add axi_inter_2x128_512_bd IP	Wade Fife	2022-02-07	3	-0/+449
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*	fpga: x400: Expand PS GPIO port for DIO control	Javier Valenzuela	2022-01-25	2	-6/+6
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*	fpga: x400: Remove stale information in register map	Humberto Jimenez	2021-07-28	1	-2/+2
\| \| \| \| \| \|	White Rabbit is not supported in X410, however the register map included an incorrect reference to this unsupported feature. This commit removes the WR reference from both the source and html files.
*	fpga: Update testbenches to work in ModelSim	Wade Fife	2021-06-17	1	-1/+1
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*	fpga: x400: Add support for X410 motherboard FPGA	Wade Fife	2021-06-10	64	-0/+17032
	Co-authored-by: Andrew Moch <Andrew.Moch@ni.com> Co-authored-by: Daniel Jepson <daniel.jepson@ni.com> Co-authored-by: Javier Valenzuela <javier.valenzuela@ni.com> Co-authored-by: Joerg Hofrichter <joerg.hofrichter@ni.com> Co-authored-by: Kumaran Subramoniam <kumaran.subramoniam@ni.com> Co-authored-by: Max Köhler <max.koehler@ni.com> Co-authored-by: Michael Auchter <michael.auchter@ni.com> Co-authored-by: Paul Butler <paul.butler@ni.com> Co-authored-by: Wade Fife <wade.fife@ettus.com> Co-authored-by: Hector Rubio <hrubio@ni.com>