uhd - Ettus' UHD Repository

	Commit message (Collapse)	Author	Age	Files	Lines
*	fpga: x400: zbx: Add support for XO3 CPLD variant.	Javier Valenzuela	2022-07-20	19	-54/+1718
\| \| \| \| \| \| \| \| \| \| \| \| \| \|	The main changes included are: - Variant-dependent pin-out instantiation. - Update clocking scheme in top level file to include XO3 PLL - Add ability to shift outgoing data for the GPIO communication interface with the X410 FPGA. - Include project files required to build the XO3 variant of the ZBX CPLD. - Add build flow for Lattice Diamond designs. - Add ability to build XO3 variant of ZBX CPLD.
*	fpga: x400: zbx: cpld: Bump ZBX regmap copyright	Javier Valenzuela	2022-02-10	11	-11/+11
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*	fpga: x400: Expand PS GPIO port for DIO control	Javier Valenzuela	2022-01-25	1	-1/+1
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*	fpga: x400: Connect Radio Blocks to DIO	Javier Valenzuela	2022-01-25	2	-74/+1
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*	fpga: x400: Refactor CPLDs build process	Humberto Jimenez	2021-12-01	16	-128/+400
\| \| \| \| \| \| \| \| \| \|	This commit refactors the X410's CPLDs build process to make it similar to other FPGA targets within the repo. The new process relies on basic Quartus build utilities. Additionally, this commit adds support for an alternative MAX10 CPLD for the motherboard CPLD implementation. Both previous (10M04) and new variant (10M08) are supported concurrently. The images package mapping is updated to reflect these changes.
*	fpga: x400: zbx: Add support for ZBX CPLD	Javier Valenzuela	2021-06-10	37	-0/+17727
	Co-authored-by: Cherwa Vang <cherwa.vang@ni.com> Co-authored-by: Martin Braun <martin.braun@ettus.com> Co-authored-by: Max Köhler <max.koehler@ni.com> Co-authored-by: Paul Butler <paul.butler@ni.com>