aboutsummaryrefslogtreecommitdiffstats
path: root/fpga/usrp3/top/x300
Commit message (Expand)AuthorAgeFilesLines
* fpga: x300: Fix time register readbackWade Fife2021-12-151-2/+2
* fpga: x300: OR ATR signals going into db_controlMartin Braun2021-12-071-1/+10
* fpga: x300: Update synchronizer constraintWade Fife2021-09-131-1/+1
* fpga: Set default part for sim in setupenv.shWade Fife2021-08-301-0/+4
* x300: Fix sfpp_io_core tuser widthWade Fife2021-08-271-1/+1
* fpga: Update testbenches to work in ModelSimWade Fife2021-06-173-7/+79
* fpga: Update rfnoc_image_core for all targetsWade Fife2021-06-104-1482/+1642
* fpga: Change RFNoC YAML version numbers to stringsWade Fife2021-06-082-4/+4
* fpga: Add Replay Block to RFNoC Core Imagemattprost2020-09-037-176/+918
* fpga: Update DRAM IO signaturesWade Fife2020-09-032-8/+8
* fpga: remove liberioRobertWalstab2020-07-201-1/+1
* fpga: Update RFNOC_EDGE_TBL_FILE for CygwinWade Fife2020-06-121-1/+1
* x300: Expand DRAM address space to 1GWade Fife2020-05-181-3/+3
* X300: Make VITA time monotonicMichael West2020-05-121-2/+2
* rfnoc: Add management filter to generic xportWade Fife2020-02-191-30/+34
* x300: add front-panel GPIO source controleklai2020-02-182-7/+45
* Merge FPGA repository back into UHD repositoryMartin Braun2020-01-28153-0/+121373
* Removed copy of FPGA source files.Martin Braun2014-10-071743-1185298/+0
* fpga: Multiple X300 FPGA bugfixes and enhancementsAshish Chaudhari2014-09-24269-292575/+13138
* fpga: Added FPGA code for X300 MIMO alignment bugfixAshish Chaudhari2014-08-195-50/+22
* fpga: Updating FPGA code for UHD-3.7.2-rc1Ben Hilburn2014-07-2241-3083/+3064
* fpga: updating b200 and x300 FPGA source code for latest imagesBen Hilburn2014-05-1420-3524/+3508
* x300 fpga: updating FPGA code with latest bug fixesBen Hilburn2014-03-206-3411/+3432
* Adding bootram.coe file from latest firmware changes.michael-west2014-03-031-2377/+2377
* Pushing the bulk of UHD-3.7.0 code.Ben Hilburn2014-02-141934-0/+1464777