uhd - Ettus' UHD Repository

	Commit message (Expand)	Author	Age	Files	Lines
*	fpga: Set default part for sim in setupenv.sh	Wade Fife	2021-08-30	1	-0/+4
*	fpga: Update rfnoc_image_core for all targets	Wade Fife	2021-06-10	3	-196/+261
*	fpga: Change RFNoC YAML version numbers to strings	Wade Fife	2021-06-08	1	-2/+2
*	fpga: e31x: Add OOT sources to Makefile.e31x.inc	Wade Fife	2020-11-13	1	-0/+8
*	fpga: e31x: Change image file to e310_rfnoc_image_core	Wade Fife	2020-09-09	3	-5/+5
*	fpga: e31x: Change RFNoC Ctrl clock to 40 MHz	Wade Fife	2020-08-19	2	-1/+3
*	fpga: e31x: Fix timeout for timekeeper registers	Wade Fife	2020-08-19	1	-180/+278
*	fpga: e310: Fix device in image core YAML	Wade Fife	2020-08-14	1	-1/+1
*	fpga, mpm: Bump FPGA compat number	RobertWalstab	2020-07-24	1	-1/+1
*	fpga: rfnoc: Fix testbenches to run under ModelSim	Wade Fife	2020-07-20	1	-3/+4
*	fpga: e31x: Add gitignore file	Martin Braun	2020-07-18	1	-0/+8
*	e31x: Minor cleanup on top-level e31x.v module	Martin Braun	2020-07-18	2	-15/+14
*	e31x: Swap out liberio for internal ethernet in the idle image	RobertWalstab	2020-07-18	1	-2/+2
*	e31x: fpga: connect device_id	RobertWalstab	2020-07-18	1	-1/+5
*	e31x: Swap out liberio for internal Ethernet	RobertWalstab	2020-07-16	5	-429/+522
*	fpga: Update RFNOC_EDGE_TBL_FILE for Cygwin	Wade Fife	2020-06-12	1	-1/+1
*	fpga: e31x: Replace symbolic link for Cygwin	Wade Fife	2020-05-12	1	-1/+1
*	fpga: e31x: Update constraints to avoid timing issues	Wade Fife	2020-04-08	1	-6/+6
*	Merge FPGA repository back into UHD repository	Martin Braun	2020-01-28	57	-0/+41040