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* images: Remove references to N230Martin Braun2022-02-151-7/+0
| | | | | | USRP N230 is no longer supported starting with UHD 4, and thus, we can remove it from the image manifest. This will no longer download N230 images when calling uhd_images_downloader from UHD 4.
* images: Add utilization report files to B2xx image filesMartin Braun2022-02-101-4/+8
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* fpga: tools: Fix adding directories for HDL sourceWade Fife2022-01-131-1/+1
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* fpga: hls: Add version to generated HLS IPWade Fife2022-01-131-2/+2
| | | | | | | | | This change causes HLS IP to be exported with a version of 1.0.0 instead of a date code. Due to a bug in Vivado, date codes after 0x7FFFFFFF (anything in 2022 or beyond) cause an error. Setting an explicit revision avoids this issue. See Xilinx AR 76960 for details.
* images: Add the utilization report for X410 images (X4_200)Martin Braun2021-12-171-1/+3
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* fpga: tools: Update Vivado scripts to use python3Wade Fife2021-12-081-4/+4
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* fpga: x400: Refactor CPLDs build processHumberto Jimenez2021-12-011-4/+8
| | | | | | | | | | This commit refactors the X410's CPLDs build process to make it similar to other FPGA targets within the repo. The new process relies on basic Quartus build utilities. Additionally, this commit adds support for an alternative MAX10 CPLD for the motherboard CPLD implementation. Both previous (10M04) and new variant (10M08) are supported concurrently. The images package mapping is updated to reflect these changes.
* fpga: tools: Add Quartus build utilitiesHumberto Jimenez2021-12-013-0/+163
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* fpga: Update help message for setupenv.shWade Fife2021-09-101-5/+7
| | | | | Updates the language in setupenv.sh --help to better reflect that there are many locations where Vivado is searched.
* fpga: tools: Add UHD_FPGA_DIR definition to synthesisWade Fife2021-09-083-6/+11
| | | | | | | | | | | | | | | | | This adds a Verilog definition named `UHD_FPGA_DIR that corresponds to the location of the UHD "fpga" directory. This allows you to include files in your out-of-tree modules relative to the FPGA directory. For example, you could include the library header file rfnoc_chdr_utils.vh using the following: `include `"`UHD_FPGA_DIR/usrp3/lib/rfnoc/core/rfnoc_chdr_utils.vh`" Some simulators may not support `" outside of the context of a `define, in which case you can do the following: `define RFNOC_CHDR_UTILS_PATH \ `"`UHD_FPGA_DIR/usrp3/lib/rfnoc/core/rfnoc_chdr_utils.vh`" `include `RFNOC_CHDR_UTILS_PATH
* fpga: Set default part for sim in setupenv.shWade Fife2021-08-301-5/+4
| | | | | | | | | This sets the ARCH and PART_ID environment variables so that the selected part family is used for simulations by default. This can be overridden by changing them in the Makefile for the testbench if a testbench requires a specific part family. Prior to this change, the default was always ARCH=kintex7, PART_ID=xc7k410t/ffg900/-2, which required support for that part to be installed.
* fpga: Fix Xilinx bitfile parser for Python 3Martin Braun2021-08-241-31/+54
| | | | | | | | | The script was previously only Python 2 compatible. Python 2 support is now removed, so we don't maintain backwards compatibility with Python 2. This also fixes all linter warnings.
* fpga: sim: Add PkgComplex, PkgMath, and PkgRandomWade Fife2021-08-081-0/+2
| | | | | | | | | | | | PkgComplex adds functions for doing complex arithmetic in SystemVerilog simulation. PkgMath provides mathematical operations and constants that aren't built into SystemVerilog, such as a constant for pi and the function round(). PkgRandom adds randomization functions beyond what standard Verilog supports but that don't require any special licenses or simulators.
* fpga: x400: Add makefiles for RF testbenchesWade Fife2021-06-171-3/+3
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* fpga: tools: Detect assertions in ModelSim simulationWade Fife2021-06-171-2/+22
| | | | | | | This change allows assertion errors/failures in ModelSim to be detected and causes ModelSim to return a non-zero value when such an assertion error occurs. This allows the return value of ModelSim to be used to determine whether or not the testbench passed.
* fpga: tools: Put SIM_SRCS at end of compile orderWade Fife2021-06-171-1/+1
| | | | | | VHDL depends on the compile order. This commit changes the order so that SIM_SRCS are compiled last with ModelSim to avoid issues with dependencies.
* fpga: tools: Support new FPGA types in viv_simulator.makWade Fife2021-06-171-2/+2
| | | | | | This updates the existing PART_NAME generation used in simulation makefiles to work with newer part families by calling viv_gen_part_id.py to generate the part name needed by Vivado.
* fpga: tools: Fix python2 reference in viv_ip_builder.makWade Fife2021-06-171-1/+1
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* fpga: tools: Add modelsim.excludesWade Fife2021-06-171-0/+18
| | | | | This is a list of testbenches that don't work with ModelSim and should be excluded when running run_testbenches.py.
* fpga: tools: Add modelsim.ini to ModelSim callsWade Fife2021-06-174-7/+38
| | | | | | | | | | | This adds the MSIM_VIV_COMPLIBDIR environment variable to specify a non-default location for the compilation libraries. This also allows a modelsim.ini other than the one in the ModelSim installation folder to be used. By default, the one in the simulation libraries compilation directory will be used. This can be changed by setting MSIM_MODELSIM_INI to the one you want to use, or set it to an empty string to use the one in the ModelSim installation folder.
* fpga: tools: Add features to run_testbenches.pyWade Fife2021-06-171-6/+19
| | | | | | | | | | | | | | | | Run "make ip" in a separate step for each testbench. This allows some testbenches to work better with ModelSim because it needs IP files that aren't known until after the IP is generated. Make run_testbenches.py more log friendly. Add a -l/--logged option for when the output is being logged. In this case, we don't want to display elapsed time every second. Add "Begin TB Log:" and "End TB Log:" to the output to more easily tell where the output from one testbench ends and another begins. Use the basedir argument as the base directory in which to search for testbenches so that a subset of the repo can be easily specified.
* fpga: tools: Add ip target to simulation makefilesWade Fife2021-06-171-2/+5
| | | | | Allow building of just the IP by running "make ip" in simulation directories.
* fpga: tools: Add X410 support for image packagingHumberto Jimenez2021-06-101-0/+24
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* fpga: x400: Add support for X410 motherboard FPGAWade Fife2021-06-101-0/+2
| | | | | | | | | | | | | Co-authored-by: Andrew Moch <Andrew.Moch@ni.com> Co-authored-by: Daniel Jepson <daniel.jepson@ni.com> Co-authored-by: Javier Valenzuela <javier.valenzuela@ni.com> Co-authored-by: Joerg Hofrichter <joerg.hofrichter@ni.com> Co-authored-by: Kumaran Subramoniam <kumaran.subramoniam@ni.com> Co-authored-by: Max Köhler <max.koehler@ni.com> Co-authored-by: Michael Auchter <michael.auchter@ni.com> Co-authored-by: Paul Butler <paul.butler@ni.com> Co-authored-by: Wade Fife <wade.fife@ettus.com> Co-authored-by: Hector Rubio <hrubio@ni.com>
* fpga: tools: Fix part selection in setupenvSam O'Brien2021-06-101-4/+12
| | | | | | | | | | | | | | The script setupenv_base.sh, which is used to setup the development environmnet in the open source toolchain, adds some functions to the shell that are used to interact with vivado. Some of the functions were looking in the wrong argument for the product name. This commit fixes the bug. In addition, supplying an incorrect part name returned a rather opaque error message. This commit also fixes the error handling so that the intended error message is displayed. Signed-off-by: Sam O'Brien <sam.obrien@ni.com>
* fpga: tools: Add ability to run commands before routeWade Fife2021-06-031-5/+11
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* fpga: tools: Add ability to patch IP during generationWade Fife2021-06-032-0/+87
| | | | | | This adds the ability to call BUILD_VIVADO_IP, as before, followed by REBUILD_VIVADO_IP_WITH_PATCH to patch a file generated by the IP and then rebuild the IP with the patched file.
* fpga: tools: Add support for RFSoCHumberto Jimenez2021-06-032-9/+9
| | | | | | | This commit includes the following changes to the tools: - Change part definition in XCI and BD editors for the RFSoC family - Resolve part name in Vivado IP management utilities with viv_gen_part_id.py
* fpga: Remove Python2 support from build systemMartin Braun2021-01-0417-119/+121
| | | | | | | - 2to3 was used to convert the Python scripts, except where the tool choked and manual intervention was required - All references to "python" where replaced with "python3" - buffer() was replaced by memoryview()
* fpga: Added AA image mappings to N320Aaron Rossetto2020-09-031-1/+6
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* fpga: rfnoc: Remove deprecated filesWade Fife2020-08-231-5/+0
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* fpga: tools: RESOLVE_PATH checks for an empty pathAndrew Moch2020-07-301-4/+4
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* fpga: lib: Add width agnostic version of Ethernet InterfaceAndrew Moch2020-06-301-0/+1
| | | | | | | | | | | | | | | | | | The rnfoc/xport section is refactored in System Verilog to allow the following improvements (1) CPU_W - Sets the size of the c2e and e2c pipes. This can be run at a different clock rate than the main ethernet pipe (2) CHDR_W - Sets the size of the v2e and e2v pipes. This can be run at a different clock rate than the main ethernet pipe (3) ENET_W - Sets the size of the eth_tx and eth_rx pipes. eth_interface_tb runs traffic from e2c,e2v,v2e,c2e simultaneously against the original xport_sv implementation, and against the new implementation with widths of 64/128/512. A chdr_management node info request queries the port info of the node0 in the eth_interface. eth_ifc_synth_test.sv can be compiled with the make xsim target to test out the size of various configurations.
* fpga: tools: Highlight suppressible errors from vlintWade Fife2020-06-291-1/+1
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* fpga: lib: Add synthesizable AXI4-Stream SV componentsAndrew Moch2020-06-251-0/+4
| | | | | | | | | | | | | | | | | | | Components are connected together with AxiStreamIfc. Some features include: (1) Add bytes to the start of a packet (2) Remove bytes from a packet (3) Wrappers for some older components a. fifo - buffer but imediately pass a packet b. packet_gate - buffer and hold till end of packet c. width_conv - cross clock domains and change width of axi bus The AxiStreamIf was moved from PkgAxiStreamBfm to its own file. It can be used to connect to ports with continuous assignment. AxiStreamPacketIf must be used procedurally but allows the following new methods: - reached_packet_byte - notify when tdata contains a paritcular byte - get_packet_byte/get_packet_field - extract a byte or field from axi - put_packet_byte/put_packet_field - overwrite a byte or field onto axi
* fpga: tools: Fix ModelSim return statusWade Fife2020-06-182-5/+12
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* fpga: tools: remove temporary Xilinx directories for BD recreationMax Köhler2020-06-151-10/+13
| | | | | | | During recreation of block diagrams any RTL modules will be kept in hidden directories within the build directory. Updates of the RTL sources might not be taken into account. Solution is to remove Xilinx's hidden project directories before calling vivado.
* fpga: tools: Allow multiple top modules with ModelSimWade Fife2020-06-111-1/+1
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* fpga: tools: Improve detection of setupenv sourcingWade Fife2020-05-281-29/+31
| | | | | This change allows detection of attempting to execute setupenv.sh rather than sourcing it, which is required.
* fpga: tools: Improve native ModelSim supportWade Fife2020-05-263-72/+255
| | | | | This adds support for colored output and support for directories added to the list of source files (for HLS support).
* fpga: tools: Add contents of directories for HDL sourceWade Fife2020-05-263-5/+26
| | | | | | | | For HLS builds, the output file names aren't known in advance. This makes it difficult to write the Makefile to pull in the files and pass them to the build tools. This change allows you to add a directory as your HDL source so that all files in the directory will be pulled in by the build process.
* fpga: tools: Remove uhd_image_builderMartin Braun2020-05-184-1244/+0
| | | | | The image builder was replaced by rfnoc_image_builder, and has been obsolete since then.
* fpga: tools: Fix HLS IP build with CygwinHumberto Jimenez2020-05-122-4/+10
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* fpga: tools: Add -voptargs=+acc to ModelSim GUIWade Fife2020-04-141-1/+1
| | | | | | Add -voptargs=+acc to the default options when running vsim. This option enables debug command access to objects in the design, which is generally needed for debugging in the GUI.
* fpga: tools: Option to check for full Vivado versionHumberto Jimenez2020-04-141-0/+24
| | | | | | | | | | | | | | | | | | | | | | This commits enables the FPGA build infrastructure to require a very specific Vivado version, all the way to the patch level. Vivado typically has the following version format: Year.release.update_patch This commit enables setupenv_base.sh to optionally look for the environment variable VIVADO_VER_FULL, which should contain the full Vivado version in the format specified above. Vivado is directly used to retrieve the installed version, returning an error if the requested version is not found. Example in setupenv.sh (which calls setupenv_base.sh): VIVADO_VER=2019.1 VIVADO_VER_FULL=2019.1.1_AR73068 The setupenv.sh script will setup Vivado 2019.1, but it will also verify that both Update 1 and patch AR73068 are installed.
* fpga: tools: Add support for .sdc in VivadoPaul Butler2020-04-021-0/+3
| | | | | | viv_utils.tcl will now read files with the .sdc suffix using the read_xdc Vivado command. This is especially useful when I/O timing constraints in the FPGA and CPLD need to depend on a common constant.
* fpga: tools: Add default Vivado install locationWade Fife2020-04-011-1/+5
| | | | | | Xilinx changed the default Vivado install location from /opt/Xilix to /tools/Xilinx. This commit adds support for finding Vivado in either the new location or the old location.
* fpga: tools: Add ModelSim to run_testbenches.pyWade Fife2020-03-231-11/+11
| | | | | This adds the "modelsim" simulator option to run_testbenches.py to allow for regression testing of the native ModelSim simulation target.
* fixup! fpga: tools: Add modelsim to make sim targetsWade Fife2020-03-231-27/+25
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* fpga: tools: Add modelsim to make sim targetsAndrew Moch2020-03-203-33/+124
| | | | | | | | | | | | | | | This adds a simulation make target that allows you to run ModelSim natively rather than through Vivado. Adds or modifies the following simulation make targets: make vlint - Brake up compilation to Verilog/SystemVerilog/VHDL make modelsim - Depends on make vlint and invokes modelsim Adds the following variables: MODELSIM_ARGS - Added to invocation of ModelSim SVLOG_ARGS - Added to SystemVerilog invocation of vlog VLOG_ARGS - Added to Verilog invocation of vlog VHDL_ARGS - Added to VHDL invocation of vcom
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