| Commit message (Expand) | Author | Age | Files | Lines |
* | fpga: Remove Python2 support from build system | Martin Braun | 2021-01-04 | 17 | -119/+121 |
* | fpga: Added AA image mappings to N320 | Aaron Rossetto | 2020-09-03 | 1 | -1/+6 |
* | fpga: rfnoc: Remove deprecated files | Wade Fife | 2020-08-23 | 1 | -5/+0 |
* | fpga: tools: RESOLVE_PATH checks for an empty path | Andrew Moch | 2020-07-30 | 1 | -4/+4 |
* | fpga: lib: Add width agnostic version of Ethernet Interface | Andrew Moch | 2020-06-30 | 1 | -0/+1 |
* | fpga: tools: Highlight suppressible errors from vlint | Wade Fife | 2020-06-29 | 1 | -1/+1 |
* | fpga: lib: Add synthesizable AXI4-Stream SV components | Andrew Moch | 2020-06-25 | 1 | -0/+4 |
* | fpga: tools: Fix ModelSim return status | Wade Fife | 2020-06-18 | 2 | -5/+12 |
* | fpga: tools: remove temporary Xilinx directories for BD recreation | Max Köhler | 2020-06-15 | 1 | -10/+13 |
* | fpga: tools: Allow multiple top modules with ModelSim | Wade Fife | 2020-06-11 | 1 | -1/+1 |
* | fpga: tools: Improve detection of setupenv sourcing | Wade Fife | 2020-05-28 | 1 | -29/+31 |
* | fpga: tools: Improve native ModelSim support | Wade Fife | 2020-05-26 | 3 | -72/+255 |
* | fpga: tools: Add contents of directories for HDL source | Wade Fife | 2020-05-26 | 3 | -5/+26 |
* | fpga: tools: Remove uhd_image_builder | Martin Braun | 2020-05-18 | 4 | -1244/+0 |
* | fpga: tools: Fix HLS IP build with Cygwin | Humberto Jimenez | 2020-05-12 | 2 | -4/+10 |
* | fpga: tools: Add -voptargs=+acc to ModelSim GUI | Wade Fife | 2020-04-14 | 1 | -1/+1 |
* | fpga: tools: Option to check for full Vivado version | Humberto Jimenez | 2020-04-14 | 1 | -0/+24 |
* | fpga: tools: Add support for .sdc in Vivado | Paul Butler | 2020-04-02 | 1 | -0/+3 |
* | fpga: tools: Add default Vivado install location | Wade Fife | 2020-04-01 | 1 | -1/+5 |
* | fpga: tools: Add ModelSim to run_testbenches.py | Wade Fife | 2020-03-23 | 1 | -11/+11 |
* | fixup! fpga: tools: Add modelsim to make sim targets | Wade Fife | 2020-03-23 | 1 | -27/+25 |
* | fpga: tools: Add modelsim to make sim targets | Andrew Moch | 2020-03-20 | 3 | -33/+124 |
* | fpga: tools: Ignore BD layout info for TCL-based BD | Humberto Jimenez | 2020-03-12 | 1 | -1/+1 |
* | Merge FPGA repository back into UHD repository | Martin Braun | 2020-01-28 | 43 | -0/+7382 |