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* fpga: sim: Add PkgComplex, PkgMath, and PkgRandomWade Fife2021-08-084-0/+544
| | | | | | | | | | | | PkgComplex adds functions for doing complex arithmetic in SystemVerilog simulation. PkgMath provides mathematical operations and constants that aren't built into SystemVerilog, such as a constant for pi and the function round(). PkgRandom adds randomization functions beyond what standard Verilog supports but that don't require any special licenses or simulators.
* fpga: sim: Check for empty packet in clear_unused_bytesWade Fife2021-06-171-0/+4
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* fpga: sim: Add slave_idle() to PkgAxiStreamBfm.svWade Fife2021-06-101-0/+4
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* fpga: lib: Add PHASE parameter to sim_clk_genWade Fife2021-06-031-1/+3
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* fpga: sim: Fix stream command and status modelsWade Fife2020-08-311-9/+9
| | | | | | | | This updates PkgChdrBfm to correct some errors when modeling stream command and stream status packets. - Fix behavior when CHDR_W = 512 - Fix assertions in read_ctrl()
* fpga: sim: Update PkgEthernetAndrew Moch2020-07-311-57/+91
| | | | | | Consolidated calcuation of last_tkeep and tkeep_last. Changed error checking to support unwrinkling tkeep/trailing changes in 100G etherent and support for testing packet dropping on backup.
* fpga: sim: Fix AxiLiteBfmAndrew Moch2020-07-311-3/+3
| | | | | AxiLiteBfm incorrectly included stb argument on rd() and printed actual response instead of expected in debug message.
* fpga: lib: Add synthesizable AXI4-Stream SV componentsAndrew Moch2020-06-254-78/+990
| | | | | | | | | | | | | | | | | | | Components are connected together with AxiStreamIfc. Some features include: (1) Add bytes to the start of a packet (2) Remove bytes from a packet (3) Wrappers for some older components a. fifo - buffer but imediately pass a packet b. packet_gate - buffer and hold till end of packet c. width_conv - cross clock domains and change width of axi bus The AxiStreamIf was moved from PkgAxiStreamBfm to its own file. It can be used to connect to ports with continuous assignment. AxiStreamPacketIf must be used procedurally but allows the following new methods: - reached_packet_byte - notify when tdata contains a paritcular byte - get_packet_byte/get_packet_field - extract a byte or field from axi - put_packet_byte/put_packet_field - overwrite a byte or field onto axi
* fpga: lib: Add interface and model for AXI4-LiteAndrew Moch2020-06-242-1/+750
| | | | | | | | | | | | | | | | | (1) Synthesizable AxiLiteIf (2) Simulation model for AxiLite contains an AxiLiteTransaction class and an AxiLiteBfm class. Important Methods a. wr - performs non-blocking write and checks for expected response b. wr_block - performs a blocking write and provides response c. rd - performs a non-blocking read and checks for expected response d. rd_block - persforms a blocking read and provides response The model allows parallel execution of reads and writes, but enforces rd and write ordering when using the above methods. When transactions are posted directly, ordering is not guaranteed, and reads and writes are put on the interface immediately.
* fpga: rfnoc: Add support for 512-bit CHDR widthsAndrew Moch2020-06-183-169/+210
| | | | | | | | This fixes the rfnoc_null_src_sink, chdr_crossbar_nxn, and chdr_stream_endpoint blocks so that wider CHDR widths are properly supported. It also updates PkgChdrBfm to able to properly test these blocks. The testbenches have been updated to test both 64 and 512-bit widths.
* fpga: sim: Add packet_info_equal functionWade Fife2020-05-283-1/+15
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* fpga: sim: Don't affect packet arguments in chdr_to_axisWade Fife2020-05-041-4/+4
| | | | | | | | This updates the chdr_to_axis method so that it doesn't change the input chdr_packet object. This is useful in case there are other references to that object in use. Not modifying the object means that you don't always have to copy the object before passing it to this method.
* fpga: sim: Fix get_slave_data_bfm methodWade Fife2020-05-041-1/+1
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* fpga: sim: Export return types in PkgRfnocBlockCtrlBfmWade Fife2020-05-041-0/+2
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* fpga: sim: Export ChdrPacket in PkgRfnoBlockCtrlBfmWade Fife2020-04-141-0/+1
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* sim: Rename class typedefsWade Fife2020-03-094-72/+72
| | | | | | | | For example, the ChdrPacket typedef is being renamed from ChdrPacket to ChdrPacket_t. This allows the code to distinguish between the unparameterized class and the already parameterized class. This isn't strictly necessary, but it makes some Vivado 2019.1 bugs easier to work around. It also makes the code slightly less ambiguous.
* sim: Add ChdrIfaceBfm testWade Fife2020-03-095-5/+675
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* sim: Add item support to RFNoC simulationWade Fife2020-03-092-34/+414
| | | | | This adds variants of the send and recv methods in RfnocBlockCtrlBfm and ChdrIfaceBfm that input/output items instead of CHDR words.
* sim: Parameterize chdr_word_t data typeWade Fife2020-03-098-208/+381
| | | | | | | | | | | | | | | | | | This replaces chdr_word_t, which was a statically defined 64-bit data type, with a paramaterizable data type that matches the defined CHDR_W. Code that formerly referenced the chdr_word_t data type can now define the data type for their desired CHDR_W and ITEM_W as follows: // Define the CHDR word and item/sample data types typedef ChdrData #(CHDR_W, ITEM_W)::chdr_word_t chdr_word_t; typedef ChdrData #(CHDR_W, ITEM_W)::item_t item_t; ITEM_W is optional when defining chdr_word_t if items are not needed. Static methods in the ChdrData class also provide the ability to convert between CHDR words and data items. For example: // Convert CHDR data buffer to a buffer of samples samples = ChdrData#(CHDR_W, ITEM_W)::chdr_to_item(data);
* sim: Split PkgRfnocBlockCtrlBfm into separate packagesWade Fife2020-03-095-400/+418
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* Merge FPGA repository back into UHD repositoryMartin Braun2020-01-2822-0/+6222
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The FPGA codebase was removed from the UHD repository in 2014 to reduce the size of the repository. However, over the last half-decade, the split between the repositories has proven more burdensome than it has been helpful. By merging the FPGA code back, it will be possible to create atomic commits that touch both FPGA and UHD codebases. Continuous integration testing is also simplified by merging the repositories, because it was previously difficult to automatically derive the correct UHD branch when testing a feature branch on the FPGA repository. This commit also updates the license files and paths therein. We are therefore merging the repositories again. Future development for FPGA code will happen in the same repository as the UHD host code and MPM code. == Original Codebase and Rebasing == The original FPGA repository will be hosted for the foreseeable future at its original local location: https://github.com/EttusResearch/fpga/ It can be used for bisecting, reference, and a more detailed history. The final commit from said repository to be merged here is 05003794e2da61cabf64dd278c45685a7abad7ec. This commit is tagged as v4.0.0.0-pre-uhd-merge. If you have changes in the FPGA repository that you want to rebase onto the UHD repository, simply run the following commands: - Create a directory to store patches (this should be an empty directory): mkdir ~/patches - Now make sure that your FPGA codebase is based on the same state as the code that was merged: cd src/fpga # Or wherever your FPGA code is stored git rebase v4.0.0.0-pre-uhd-merge Note: The rebase command may look slightly different depending on what exactly you're trying to rebase. - Create a patch set for your changes versus v4.0.0.0-pre-uhd-merge: git format-patch v4.0.0.0-pre-uhd-merge -o ~/patches Note: Make sure that only patches are stored in your output directory. It should otherwise be empty. Make sure that you picked the correct range of commits, and only commits you wanted to rebase were exported as patch files. - Go to the UHD repository and apply the patches: cd src/uhd # Or wherever your UHD repository is stored git am --directory fpga ~/patches/* rm -rf ~/patches # This is for cleanup == Contributors == The following people have contributed mainly to these files (this list is not complete): Co-authored-by: Alex Williams <alex.williams@ni.com> Co-authored-by: Andrej Rode <andrej.rode@ettus.com> Co-authored-by: Ashish Chaudhari <ashish@ettus.com> Co-authored-by: Ben Hilburn <ben.hilburn@ettus.com> Co-authored-by: Ciro Nishiguchi <ciro.nishiguchi@ni.com> Co-authored-by: Daniel Jepson <daniel.jepson@ni.com> Co-authored-by: Derek Kozel <derek.kozel@ettus.com> Co-authored-by: EJ Kreinar <ej@he360.com> Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com> Co-authored-by: Ian Buckley <ian.buckley@gmail.com> Co-authored-by: Jörg Hofrichter <joerg.hofrichter@ni.com> Co-authored-by: Jon Kiser <jon.kiser@ni.com> Co-authored-by: Josh Blum <josh@joshknows.com> Co-authored-by: Jonathon Pendlum <jonathan.pendlum@ettus.com> Co-authored-by: Martin Braun <martin.braun@ettus.com> Co-authored-by: Matt Ettus <matt@ettus.com> Co-authored-by: Michael West <michael.west@ettus.com> Co-authored-by: Moritz Fischer <moritz.fischer@ettus.com> Co-authored-by: Nick Foster <nick@ettus.com> Co-authored-by: Nicolas Cuervo <nicolas.cuervo@ettus.com> Co-authored-by: Paul Butler <paul.butler@ni.com> Co-authored-by: Paul David <paul.david@ettus.com> Co-authored-by: Ryan Marlow <ryan.marlow@ettus.com> Co-authored-by: Sugandha Gupta <sugandha.gupta@ettus.com> Co-authored-by: Sylvain Munaut <tnt@246tNt.com> Co-authored-by: Trung Tran <trung.tran@ettus.com> Co-authored-by: Vidush Vishwanath <vidush.vishwanath@ettus.com> Co-authored-by: Wade Fife <wade.fife@ettus.com>
* Removed copy of FPGA source files.Martin Braun2014-10-0727-2901/+0
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* Pushing the bulk of UHD-3.7.0 code.Ben Hilburn2014-02-1427-0/+2901
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