aboutsummaryrefslogtreecommitdiffstats
path: root/fpga/usrp3/lib
Commit message (Expand)AuthorAgeFilesLines
* fpga: e320: Improve timing on LVDS interfaceWade Fife2020-12-113-355/+539
* fpga: lib: add glitch free mux moduleMax Köhler2020-12-032-0/+30
* fpga: lib: Fix axis_strm_monitor parametersWade Fife2020-10-201-2/+2
* fpga: lib: Fix small packets stuck in 10 GbE TXAndrew Moch2020-10-051-3/+17
* fpga: lib: Fix 10 GbE cut-through modeAndrew Moch2020-09-161-4/+16
* fpga: lib: add generic to disable bitq engine tri-statingMax Köhler2020-09-162-11/+16
* fpga: sim: chdr_stream_endpoint_tb improvementsWade Fife2020-08-312-36/+150
* fpga: rfnoc: Update CHDR stream INIT commandWade Fife2020-08-281-3/+10
* fpga: lib: Fix lint warningsWade Fife2020-08-283-3/+3
* fpga: rfnoc: Remove deprecated filesWade Fife2020-08-2322-2674/+5
* fpga: lib: Add more CtrlPort constantsWade Fife2020-08-191-7/+12
* fpga: lib: Add ctrlport_to_regport bridgeWade Fife2020-08-192-0/+91
* fpga: rfnoc: Enable clean switch in SwitchboardWade Fife2020-08-131-1/+1
* fpga: lib: Fix SWITCH_ON_LAST in axi_mux_selectWade Fife2020-08-131-18/+39
* fpga: lib: add handshake to replace FIFO for ctrlport CDCMax Köhler2020-08-133-48/+143
* fpga: rfnoc: Fix clock crossing in axis_data_to_chdrWade Fife2020-08-121-69/+89
* fpga: lib: Change max FFT size to 1024Wade Fife2020-08-111-2/+2
* fpga: rfnoc: Add tests to FFT blockWade Fife2020-08-102-39/+202
* fpga: lib: add Intel MAX10 architecture for 2clk FIFOMax Köhler2020-08-062-28/+33
* fpga: lib: Update xport_svAndrew Moch2020-08-056-182/+437
* fpga: rfnoc: Add RFNoC Keep One in N blockAaron Rossetto2020-08-057-0/+1432
* fpga: rfnoc: Add RFNoC Replay blockWade Fife2020-08-0411-875/+4101
* fpga: rfnoc: Add 4 KiB boundary check to sim_axi_ramWade Fife2020-08-041-0/+12
* fpga: rfnoc: Add support for CHDR_W < ITEM_W*NIPCWade Fife2020-08-042-137/+195
* fpga: lib: Fix comments and indentation in axi_fifo_short.vWade Fife2020-08-041-98/+87
* fpga: lib: Add xge features for new xport_svAndrew Moch2020-07-311-100/+191
* fpga: lib: Update AxiLiteIfAndrew Moch2020-07-311-1/+74
* fpga: lib: Fix chdr_mgmt_pkt_handler when CHDR_W != 64Andrew Moch2020-07-301-1/+1
* fpga: rfnoc: Add Signal Generator RFNoC blockWade Fife2020-07-3012-18/+1925
* fpga: lib: Add axis_packetize moduleWade Fife2020-07-302-0/+162
* fpga: Add Switchboard RFNoC blockJesse Zhang2020-07-307-0/+1121
* TwinRX: Fix increased noise floormichael-west2020-07-211-1/+1
* fpga: remove liberioRobertWalstab2020-07-203-126/+2
* fpga: rfnoc: Fix testbenches to run under ModelSimWade Fife2020-07-208-86/+64
* fpga: rfnoc: Add RFNoC Moving Average blockWade Fife2020-07-168-0/+1587
* fpga: lib: modify ctrlport decoder to Verilog 2001 compatible syntaxMax Köhler2020-07-101-39/+41
* fpga: lib: Add width agnostic version of Ethernet InterfaceAndrew Moch2020-06-3013-0/+3339
* fpga: rfnoc: Add Log-Power blockWade Fife2020-06-296-0/+1006
* fpga: rfnoc: Fix chdr_update_length functionWade Fife2020-06-291-1/+1
* fpga: rfnoc: Add RFNoC Window blockWade Fife2020-06-298-0/+1454
* fpga: lib: Fix axi_packet_gate RAM dib widthWade Fife2020-06-291-1/+1
* fpga: lib: Add features to axi_lite.vhAndrew Moch2020-06-261-23/+62
* fpga: lib: Add synthesizable AXI4-Stream SV componentsAndrew Moch2020-06-2515-0/+3201
* fpga: rfnoc: Fix read suppression test in rfnoc_block_axi_ram_fifo_tbWade Fife2020-06-251-8/+16
* fpga: lib: Add interface and model for AXI4-LiteAndrew Moch2020-06-244-0/+349
* fpga: lib: Pipeline and add clken to ip_hdr_checksumAndrew Moch2020-06-244-66/+51
* fpga: rfnoc: Add support for 512-bit CHDR widthsAndrew Moch2020-06-1816-220/+358
* fpga: lib: add extended spi core for 64bitMax Köhler2020-06-172-0/+287
* fpga: lib: extend wb_spi ability to limit transmission lengthMax Köhler2020-06-041-3/+9
* fpga: lib: Fix writes in axil_regport_masterAndrew Moch2020-06-041-23/+43
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-30 19:37:28 +0000