uhd - Ettus' UHD Repository

	Commit message (Expand)	Author	Age	Files	Lines
*	rfnoc: Add RFNoC fosphor block	Wade Fife	2020-04-14	7	-1/+1585
*	fpga: rfnoc: Add option to sample sideband info at start of packet	Wade Fife	2020-04-14	1	-58/+117
*	fpga: core: Add chdr_update_length function	Wade Fife	2020-04-14	1	-0/+21
*	fpga: lib: Add AXI-Stream splitter (axis_split)	Wade Fife	2020-04-14	2	-0/+129
*	fpga: rfnoc: Add gate to dynamically enable control-port interfaces	Max Köhler	2020-04-01	1	-0/+91
*	fpga: rfnoc: ctrport_combiner with deterministic latency for PRIORITY=1	Max Köhler	2020-04-01	1	-13/+51
*	fpga: Fix errors found by linting with vsim	Andrew Moch	2020-03-23	6	-19/+22
*	sim: Add item support to RFNoC simulation	Wade Fife	2020-03-09	6	-6/+6
*	sim: Parameterize chdr_word_t data type	Wade Fife	2020-03-09	8	-8/+30
*	fpga: lib: Modify for loop to Verilog 2001 syntax	Max Köhler	2020-03-09	1	-34/+35
*	rfnoc: Fix FIR and AXI RAM block register documentation	Wade Fife	2020-03-05	2	-9/+11
*	rfnoc: Add management filter to generic xport	Wade Fife	2020-02-19	3	-71/+138
*	radio: Update TB to use new block ctrl connect	Wade Fife	2020-02-19	1	-41/+17
*	rfnoc: Update blocks to use autogenerated noc_shell	Wade Fife	2020-02-06	23	-1825/+2407
*	fixup! lib: add option for output register in pps generator	Humberto Jimenez	2020-02-05	1	-1/+1
*	lib: add option for output register in pps generator	Max Köhler	2020-01-28	1	-2/+23
*	Merge FPGA repository back into UHD repository	Martin Braun	2020-01-28	998	-0/+583091
*	Removed copy of FPGA source files.	Martin Braun	2014-10-07	313	-168710/+0
*	fpga: Multiple X300 FPGA bugfixes and enhancements	Ashish Chaudhari	2014-09-24	6	-221/+322
*	fpga: Updating FPGA code for UHD-3.7.2-rc1	Ben Hilburn	2014-07-22	4	-21/+52
*	fpga: updating b200 and x300 FPGA source code for latest images	Ben Hilburn	2014-05-14	6	-499/+531
*	Pushing the bulk of UHD-3.7.0 code.	Ben Hilburn	2014-02-14	228	-1027/+21529
*	b2xx: Updating FPGA source with recent bugfixes.	Ben Hilburn	2013-12-03	79	-470/+1572
*	Squashed B200 FPGA Source. Code from Josh Blum, Ian Buckley, and Matt Ettus.	Ben Hilburn	2013-10-10	157	-0/+146942