aboutsummaryrefslogtreecommitdiffstats
path: root/fpga/usrp3/lib
Commit message (Expand)AuthorAgeFilesLines
* fpga: lib: Update example constraint in synchronizerWade Fife2021-09-131-18/+40
* fpga: Remove stale references to UHD_FPGA_DIRWade Fife2021-09-087-14/+7
* sim: Update chdr_16sc_to_sc12 testbenchmichael-west2021-08-101-137/+159
* fpga: Re-order error and data packetsmichael-west2021-08-101-2/+28
* fpga: Fix sc16 to sc12 convertermichael-west2021-08-101-62/+80
* fpga: rfnoc: Fix EOB loss in DUCWade Fife2021-08-087-218/+1858
* fpga: lib: Clean up and document lib filesWade Fife2021-08-083-246/+411
* rfnoc: duc: Remove stale references to CORDICWade Fife2021-08-081-18/+15
* fpga: Update testbenches to work in ModelSimWade Fife2021-06-173-47/+71
* fpga: lib: Update register comments in eth_regs.vhWade Fife2021-06-101-1/+5
* fpga: lib: Add modports to SV AXI-Stream blocksWade Fife2021-06-034-8/+8
* fpga: lib: Add time_increment port to timekeeperWade Fife2021-06-031-17/+43
* fpga: lib: Pipeline ctrlport_timerWade Fife2021-06-031-24/+81
* fpga: lib: Add clock domain comments to interfacesWade Fife2021-06-037-13/+28
* fpga: lib: Add 2 to 1 gearbox moduleWade Fife2021-06-035-0/+517
* fpga: lib: Add AXI4 (full) interfaceAndrew Moch2021-06-034-0/+619
* fpga: lib: add pause support to ethernet xportAndrew Moch2021-06-036-7/+112
* fpga: lib: Add eth_ipv4_internalWade Fife2021-06-032-0/+442
* fpga: lib: Add zynquplus family to axi_bitqHumberto Jimenez2021-06-031-12/+13
* fpga: lib: Minor cleanup of axi_lite.vhLars Amsel2021-06-031-2/+23
* fpga: rfnoc: Add ability to disable output flow controlWade Fife2021-04-142-7/+22
* fpga: lib: Add rx_front_end_gen3 testbenchWade Fife2021-04-092-0/+247
* fpga: lib: Update round_sd to eliminate X from simulationWade Fife2021-04-091-14/+45
* fpga: lib: Fix simulation of axi_fir_filterWade Fife2021-04-091-1/+1
* TwinRX: Remove frontend filtermichael-west2021-04-081-59/+8
* fpga: docs: Improve documentation of rx_frontend_gen3Martin Braun2021-04-071-1/+73
* fpga: lib: Fix DDS_SIN_COS_LUT outputs in makefilePaul Butler2021-03-311-1/+1
* fpga: dsp: Fix formatting of rx_dcoffset and add docsMartin Braun2021-03-091-38/+110
* fpga: e320: Improve timing on LVDS interfaceWade Fife2020-12-113-355/+539
* fpga: lib: add glitch free mux moduleMax Köhler2020-12-032-0/+30
* fpga: lib: Fix axis_strm_monitor parametersWade Fife2020-10-201-2/+2
* fpga: lib: Fix small packets stuck in 10 GbE TXAndrew Moch2020-10-051-3/+17
* fpga: lib: Fix 10 GbE cut-through modeAndrew Moch2020-09-161-4/+16
* fpga: lib: add generic to disable bitq engine tri-statingMax Köhler2020-09-162-11/+16
* fpga: sim: chdr_stream_endpoint_tb improvementsWade Fife2020-08-312-36/+150
* fpga: rfnoc: Update CHDR stream INIT commandWade Fife2020-08-281-3/+10
* fpga: lib: Fix lint warningsWade Fife2020-08-283-3/+3
* fpga: rfnoc: Remove deprecated filesWade Fife2020-08-2322-2674/+5
* fpga: lib: Add more CtrlPort constantsWade Fife2020-08-191-7/+12
* fpga: lib: Add ctrlport_to_regport bridgeWade Fife2020-08-192-0/+91
* fpga: rfnoc: Enable clean switch in SwitchboardWade Fife2020-08-131-1/+1
* fpga: lib: Fix SWITCH_ON_LAST in axi_mux_selectWade Fife2020-08-131-18/+39
* fpga: lib: add handshake to replace FIFO for ctrlport CDCMax Köhler2020-08-133-48/+143
* fpga: rfnoc: Fix clock crossing in axis_data_to_chdrWade Fife2020-08-121-69/+89
* fpga: lib: Change max FFT size to 1024Wade Fife2020-08-111-2/+2
* fpga: rfnoc: Add tests to FFT blockWade Fife2020-08-102-39/+202
* fpga: lib: add Intel MAX10 architecture for 2clk FIFOMax Köhler2020-08-062-28/+33
* fpga: lib: Update xport_svAndrew Moch2020-08-056-182/+437
* fpga: rfnoc: Add RFNoC Keep One in N blockAaron Rossetto2020-08-057-0/+1432
* fpga: rfnoc: Add RFNoC Replay blockWade Fife2020-08-0411-875/+4101
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-28 14:38:39 +0000