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* fpga: rfnoc: Change AWIDTH default for axi_ram_fifoWade Fife2022-02-101-1/+1
| | | | | Change AWIDTH to be the same as MEM_ADDR_W by default. Current USRPs assume the AXI address width is the same as MEM_ADDR_W.
* fpga: rfnoc: Add BLANK_OUTPUT to FIR filter block's parametersJonathon Pendlum2022-02-103-11/+20
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* fpga: Remove noc_shell_regs.vh and sim_rfnoc_lib.svhMartin Braun2022-01-254-28/+1
| | | | | Both files are a UHD 3 remnant and potentially confusing for UHD 4 codebase readers.
* fpga: x400: Connect Radio Blocks to DIOJavier Valenzuela2022-01-252-0/+74
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* uhd: update git://github.com references to httpsSteven Koo2022-01-113-13/+13
| | | | | | | GitHub is removing support for using git://. Switch to https. https://github.blog/2021-09-01-improving-git-protocol-security-github/ Signed-off-by: Steven Koo <steven.koo@ni.com>
* rfnoc: Fix noc_shell direction commentsWade Fife2021-12-0818-81/+86
| | | | | | Some comments describing data flow direction were wrong. This commit updates the Mako files and updates the noc_shell modules with newly generated versions.
* fpga: Add ability to get time from Radio blockmichael-west2021-11-173-2/+26
| | | | | | Added registers to read back radio time. Bumped minor compat. Signed-off-by: michael-west <michael.west@ettus.com>
* fpga: rfnoc: Add RFNoC CHDR resize moduleWade Fife2021-11-047-0/+2031
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* fpga: rfnoc: Add CHDR management util functionsWade Fife2021-11-041-4/+85
| | | | Add missing chdr_mgmt_*() and enum_to_chdr_w() functions.
* fpga: lib: Clean up axi_muxWade Fife2021-10-281-91/+160
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* fpga: rfnoc: Add labels to axi_switch generate blocksWade Fife2021-10-281-36/+67
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* fpga: rfnoc: Add labels to chdr_mgmt_pkt_handlerWade Fife2021-10-281-30/+45
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* fpga: rfnoc: Add documentation to chdr_xb_routing_tableWade Fife2021-10-281-46/+84
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* siggen: Fix direction of rotationWade Fife2021-10-274-35/+44
| | | | | | | | | The I and Q were swapped in sine_tone, which caused confusion and made the rotation of REG_CARTESIAN clockwise by default. This effectively made the resulting frequency negative. This PR makes the I and Q order consistent with RFNoC and fixes the direction of rotation so that a positive value for REG_PHASE_INC (phase increment) results in a counter-clockwise rotation, which yields a positive frequency.
* fpga: lib: Update example constraint in synchronizerWade Fife2021-09-131-18/+40
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* fpga: Remove stale references to UHD_FPGA_DIRWade Fife2021-09-087-14/+7
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* sim: Update chdr_16sc_to_sc12 testbenchmichael-west2021-08-101-137/+159
| | | | | | | Modified to send 2 packets back to back at each packet size to test output during sequential input packets. Also fixed whitespace. Signed-off-by: michael-west <michael.west@ettus.com>
* fpga: Re-order error and data packetsmichael-west2021-08-101-2/+28
| | | | | | | Added delay to error packets so overrun error is back in-band. Avoids dropping good data packets in the case of an overrun. Signed-off-by: michael-west <michael.west@ettus.com>
* fpga: Fix sc16 to sc12 convertermichael-west2021-08-101-62/+80
| | | | | | | | | Re-wrote converter to remove clock cycle delay on i_tready when handling residual output and fixed improper handling of tlast during residual data processing. Resolves some USB overflow issues when using sc12 data type on B200 devices. Signed-off-by: michael-west <michael.west@ettus.com>
* fpga: rfnoc: Fix EOB loss in DUCWade Fife2021-08-087-218/+1858
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | There were some rare corner cases where the EOB could get lost in the DUC due to the dds_timed logic not always passing it through as it should. This resulted in an underflow error message at the end of transmission. This commit also fixes an issue where part of the last packet used a frequency shift of 0 instead of the requested frequency shift, and an issue where the first few samples of a burst used the wrong frequency shift value. Part of the fix includes adding a TUSER port to dds_sin_cos_lut_only. The TUSER port is built into the IP but was disabled. It is now enabled and set to 1 bit wide. This has a very small effect on resource usage and can be left unconnected when not needed. The dds_freq_tune block was shared by the DUC and DDC. To avoid affecting the DDC, a new version, dds_freq_tune_duc, is being added for the DUC to use that has the necessary fixes. The new dds_wrapper.v is a wrapper for the dds_sin_cos_lut_only IP. This IP has the undesirable behavior that new inputs must be provided to push previous outputs through the IP. This wrapper hides that complexity by adding some logic to ensure all data gets pushed through automatically. This logic uses the TUSER port on the IP. Finally, a testbench for dds_timed was added.
* fpga: lib: Clean up and document lib filesWade Fife2021-08-083-246/+411
| | | | Clean-up and document axi_tag_time, dds_freq_tune, and axi_sync.
* rfnoc: duc: Remove stale references to CORDICWade Fife2021-08-081-18/+15
| | | | | Updated some comments that still referenced the old CORDIC implementation, which is no longer used.
* fpga: Update testbenches to work in ModelSimWade Fife2021-06-173-47/+71
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* fpga: lib: Update register comments in eth_regs.vhWade Fife2021-06-101-1/+5
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* fpga: lib: Add modports to SV AXI-Stream blocksWade Fife2021-06-034-8/+8
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* fpga: lib: Add time_increment port to timekeeperWade Fife2021-06-031-17/+43
| | | | | Adds a time_increment port for situations in which the parameter TIME_INCREMENT can't be used. They offer the same behavior.
* fpga: lib: Pipeline ctrlport_timerWade Fife2021-06-031-24/+81
| | | | | | | This pipelines ctrlport_timer to eliminate the long combinational path caused by the time comparisons. This change also removes the PRECISION_BITS parameter and converts it to a signal named time_ignore_bits.
* fpga: lib: Add clock domain comments to interfacesWade Fife2021-06-037-13/+28
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* fpga: lib: Add 2 to 1 gearbox moduleWade Fife2021-06-035-0/+517
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* fpga: lib: Add AXI4 (full) interfaceAndrew Moch2021-06-034-0/+619
| | | | | Add a SystemVerilog interface for connecting AXI4 ports, and an associated header file with helper macros.
* fpga: lib: add pause support to ethernet xportAndrew Moch2021-06-036-7/+112
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* fpga: lib: Add eth_ipv4_internalWade Fife2021-06-032-0/+442
| | | | | This adds a generic version of eth_internal that allows you to specify the CHDR width.
* fpga: lib: Add zynquplus family to axi_bitqHumberto Jimenez2021-06-031-12/+13
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* fpga: lib: Minor cleanup of axi_lite.vhLars Amsel2021-06-031-2/+23
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* fpga: rfnoc: Add ability to disable output flow controlWade Fife2021-04-142-7/+22
| | | | | | | | | | | | | Per the RFNoC specification, if we set the frequency of flow control updates to 0 then the input stream will not send flow control status updates to the output stream handler. This change makes it so that when the frequency of flow control status updates is configured to be zero in the FPGA output stream handler (i.e., cfg_fc_freq_bytes and cfg_fc_freq_pkts are both 0 in chdr_stream_output) then the output stream handler will not use flow control. That is, chdr_stream_output will not expect stream status updates and will not restrict output packets.
* fpga: lib: Add rx_front_end_gen3 testbenchWade Fife2021-04-092-0/+247
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* fpga: lib: Update round_sd to eliminate X from simulationWade Fife2021-04-091-14/+45
| | | | | | | | | | | | The asynchronous feedback loop on the err signal causes X to get stuck on the sum signal when simulating. This change adds a check for simulation only to force X to 0 so that unknown inputs get resolved once the inputs are known. Also added default values to the ports out and strobe_out, since having them uninitialized and without reset was causing simulation issues in other modules. The FPGA will initialize them to 0, so this change makes the code equivalent to real hardware behavior.
* fpga: lib: Fix simulation of axi_fir_filterWade Fife2021-04-091-1/+1
| | | | | | The always(*) block was never executing in some simulators because there were no signals on the right-hand side in the block. Changing it to an initial block ensures it always runs.
* TwinRX: Remove frontend filtermichael-west2021-04-081-59/+8
| | | | | | | | | | Removing the FIR filter in the frontend to reclaim resources and remove redundancy when using a DDC block. The default image has a DDC block, so only users making custom RFNoC images and using TwinRX will need to take care to properly downconvert the full bandwidth coming from the radio block. Signed-off-by: michael-west <michael.west@ettus.com>
* fpga: docs: Improve documentation of rx_frontend_gen3Martin Braun2021-04-071-1/+73
| | | | Also fixes a typo in the calibration manual page.
* fpga: lib: Fix DDS_SIN_COS_LUT outputs in makefilePaul Butler2021-03-311-1/+1
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* fpga: dsp: Fix formatting of rx_dcoffset and add docsMartin Braun2021-03-091-38/+110
| | | | | - Adapt to coding guide - Add header that explains the module
* fpga: e320: Improve timing on LVDS interfaceWade Fife2020-12-113-355/+539
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* fpga: lib: add glitch free mux moduleMax Köhler2020-12-032-0/+30
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* fpga: lib: Fix axis_strm_monitor parametersWade Fife2020-10-201-2/+2
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* fpga: lib: Fix small packets stuck in 10 GbE TXAndrew Moch2020-10-051-3/+17
| | | | | | Any packet less than CUT_THROUGH bytes has a high chance of getting stuck in the TX FIFO of the xge_mac_wrapper. In cut-through mode we were waiting for CUT_THROUGH bytes before transmitting the packet.
* fpga: lib: Fix 10 GbE cut-through modeAndrew Moch2020-09-161-4/+16
| | | | | | | When operating in cut-through mode the hold off from the MAC was not applying back pressure, so when the TX interface filled up, data was dropped. This bug was introduced when cut-through was added, and does not impact the original implementation.
* fpga: lib: add generic to disable bitq engine tri-statingMax Köhler2020-09-162-11/+16
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* fpga: sim: chdr_stream_endpoint_tb improvementsWade Fife2020-08-312-36/+150
| | | | | | | - Adds test coverage for stream command and status packets - Cleans up report output during simulation - Stops clocks at the end of simulation, so chdr_stream_endpoint_tb can be run directly instead of just chdr_stream_endpoint_all_tb
* fpga: rfnoc: Update CHDR stream INIT commandWade Fife2020-08-281-3/+10
| | | | | | This changes the behavior of the stream command with the INIT OpCode such that sending the command with 0 for the values causes no flow control stream status packets to be sent in response to incoming data.
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