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* fpga: rfnoc: Change AWIDTH default for axi_ram_fifoWade Fife2022-02-101-1/+1
* fpga: rfnoc: Add BLANK_OUTPUT to FIR filter block's parametersJonathon Pendlum2022-02-103-11/+20
* fpga: Remove noc_shell_regs.vh and sim_rfnoc_lib.svhMartin Braun2022-01-254-28/+1
* fpga: x400: Connect Radio Blocks to DIOJavier Valenzuela2022-01-252-0/+74
* uhd: update git://github.com references to httpsSteven Koo2022-01-113-13/+13
* rfnoc: Fix noc_shell direction commentsWade Fife2021-12-0818-81/+86
* fpga: Add ability to get time from Radio blockmichael-west2021-11-173-2/+26
* fpga: rfnoc: Add RFNoC CHDR resize moduleWade Fife2021-11-047-0/+2031
* fpga: rfnoc: Add CHDR management util functionsWade Fife2021-11-041-4/+85
* fpga: lib: Clean up axi_muxWade Fife2021-10-281-91/+160
* fpga: rfnoc: Add labels to axi_switch generate blocksWade Fife2021-10-281-36/+67
* fpga: rfnoc: Add labels to chdr_mgmt_pkt_handlerWade Fife2021-10-281-30/+45
* fpga: rfnoc: Add documentation to chdr_xb_routing_tableWade Fife2021-10-281-46/+84
* siggen: Fix direction of rotationWade Fife2021-10-274-35/+44
* fpga: lib: Update example constraint in synchronizerWade Fife2021-09-131-18/+40
* fpga: Remove stale references to UHD_FPGA_DIRWade Fife2021-09-087-14/+7
* sim: Update chdr_16sc_to_sc12 testbenchmichael-west2021-08-101-137/+159
* fpga: Re-order error and data packetsmichael-west2021-08-101-2/+28
* fpga: Fix sc16 to sc12 convertermichael-west2021-08-101-62/+80
* fpga: rfnoc: Fix EOB loss in DUCWade Fife2021-08-087-218/+1858
* fpga: lib: Clean up and document lib filesWade Fife2021-08-083-246/+411
* rfnoc: duc: Remove stale references to CORDICWade Fife2021-08-081-18/+15
* fpga: Update testbenches to work in ModelSimWade Fife2021-06-173-47/+71
* fpga: lib: Update register comments in eth_regs.vhWade Fife2021-06-101-1/+5
* fpga: lib: Add modports to SV AXI-Stream blocksWade Fife2021-06-034-8/+8
* fpga: lib: Add time_increment port to timekeeperWade Fife2021-06-031-17/+43
* fpga: lib: Pipeline ctrlport_timerWade Fife2021-06-031-24/+81
* fpga: lib: Add clock domain comments to interfacesWade Fife2021-06-037-13/+28
* fpga: lib: Add 2 to 1 gearbox moduleWade Fife2021-06-035-0/+517
* fpga: lib: Add AXI4 (full) interfaceAndrew Moch2021-06-034-0/+619
* fpga: lib: add pause support to ethernet xportAndrew Moch2021-06-036-7/+112
* fpga: lib: Add eth_ipv4_internalWade Fife2021-06-032-0/+442
* fpga: lib: Add zynquplus family to axi_bitqHumberto Jimenez2021-06-031-12/+13
* fpga: lib: Minor cleanup of axi_lite.vhLars Amsel2021-06-031-2/+23
* fpga: rfnoc: Add ability to disable output flow controlWade Fife2021-04-142-7/+22
* fpga: lib: Add rx_front_end_gen3 testbenchWade Fife2021-04-092-0/+247
* fpga: lib: Update round_sd to eliminate X from simulationWade Fife2021-04-091-14/+45
* fpga: lib: Fix simulation of axi_fir_filterWade Fife2021-04-091-1/+1
* TwinRX: Remove frontend filtermichael-west2021-04-081-59/+8
* fpga: docs: Improve documentation of rx_frontend_gen3Martin Braun2021-04-071-1/+73
* fpga: lib: Fix DDS_SIN_COS_LUT outputs in makefilePaul Butler2021-03-311-1/+1
* fpga: dsp: Fix formatting of rx_dcoffset and add docsMartin Braun2021-03-091-38/+110
* fpga: e320: Improve timing on LVDS interfaceWade Fife2020-12-113-355/+539
* fpga: lib: add glitch free mux moduleMax Köhler2020-12-032-0/+30
* fpga: lib: Fix axis_strm_monitor parametersWade Fife2020-10-201-2/+2
* fpga: lib: Fix small packets stuck in 10 GbE TXAndrew Moch2020-10-051-3/+17
* fpga: lib: Fix 10 GbE cut-through modeAndrew Moch2020-09-161-4/+16
* fpga: lib: add generic to disable bitq engine tri-statingMax Köhler2020-09-162-11/+16
* fpga: sim: chdr_stream_endpoint_tb improvementsWade Fife2020-08-312-36/+150
* fpga: rfnoc: Update CHDR stream INIT commandWade Fife2020-08-281-3/+10
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