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* fpga: rfnoc: Add ability to disable output flow controlWade Fife2021-04-142-7/+22
| | | | | | | | | | | | | Per the RFNoC specification, if we set the frequency of flow control updates to 0 then the input stream will not send flow control status updates to the output stream handler. This change makes it so that when the frequency of flow control status updates is configured to be zero in the FPGA output stream handler (i.e., cfg_fc_freq_bytes and cfg_fc_freq_pkts are both 0 in chdr_stream_output) then the output stream handler will not use flow control. That is, chdr_stream_output will not expect stream status updates and will not restrict output packets.
* fpga: lib: Add rx_front_end_gen3 testbenchWade Fife2021-04-092-0/+247
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* fpga: lib: Update round_sd to eliminate X from simulationWade Fife2021-04-091-14/+45
| | | | | | | | | | | | The asynchronous feedback loop on the err signal causes X to get stuck on the sum signal when simulating. This change adds a check for simulation only to force X to 0 so that unknown inputs get resolved once the inputs are known. Also added default values to the ports out and strobe_out, since having them uninitialized and without reset was causing simulation issues in other modules. The FPGA will initialize them to 0, so this change makes the code equivalent to real hardware behavior.
* fpga: lib: Fix simulation of axi_fir_filterWade Fife2021-04-091-1/+1
| | | | | | The always(*) block was never executing in some simulators because there were no signals on the right-hand side in the block. Changing it to an initial block ensures it always runs.
* TwinRX: Remove frontend filtermichael-west2021-04-081-59/+8
| | | | | | | | | | Removing the FIR filter in the frontend to reclaim resources and remove redundancy when using a DDC block. The default image has a DDC block, so only users making custom RFNoC images and using TwinRX will need to take care to properly downconvert the full bandwidth coming from the radio block. Signed-off-by: michael-west <michael.west@ettus.com>
* fpga: docs: Improve documentation of rx_frontend_gen3Martin Braun2021-04-071-1/+73
| | | | Also fixes a typo in the calibration manual page.
* fpga: lib: Fix DDS_SIN_COS_LUT outputs in makefilePaul Butler2021-03-311-1/+1
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* fpga: dsp: Fix formatting of rx_dcoffset and add docsMartin Braun2021-03-091-38/+110
| | | | | - Adapt to coding guide - Add header that explains the module
* fpga: e320: Improve timing on LVDS interfaceWade Fife2020-12-113-355/+539
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* fpga: lib: add glitch free mux moduleMax Köhler2020-12-032-0/+30
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* fpga: lib: Fix axis_strm_monitor parametersWade Fife2020-10-201-2/+2
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* fpga: lib: Fix small packets stuck in 10 GbE TXAndrew Moch2020-10-051-3/+17
| | | | | | Any packet less than CUT_THROUGH bytes has a high chance of getting stuck in the TX FIFO of the xge_mac_wrapper. In cut-through mode we were waiting for CUT_THROUGH bytes before transmitting the packet.
* fpga: lib: Fix 10 GbE cut-through modeAndrew Moch2020-09-161-4/+16
| | | | | | | When operating in cut-through mode the hold off from the MAC was not applying back pressure, so when the TX interface filled up, data was dropped. This bug was introduced when cut-through was added, and does not impact the original implementation.
* fpga: lib: add generic to disable bitq engine tri-statingMax Köhler2020-09-162-11/+16
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* fpga: sim: chdr_stream_endpoint_tb improvementsWade Fife2020-08-312-36/+150
| | | | | | | - Adds test coverage for stream command and status packets - Cleans up report output during simulation - Stops clocks at the end of simulation, so chdr_stream_endpoint_tb can be run directly instead of just chdr_stream_endpoint_all_tb
* fpga: rfnoc: Update CHDR stream INIT commandWade Fife2020-08-281-3/+10
| | | | | | This changes the behavior of the stream command with the INIT OpCode such that sending the command with 0 for the values causes no flow control stream status packets to be sent in response to incoming data.
* fpga: lib: Fix lint warningsWade Fife2020-08-283-3/+3
| | | | | Fixes various synthesis/simulation warnings that were being generated due to incorrectly sized constants.
* fpga: rfnoc: Remove deprecated filesWade Fife2020-08-2322-2674/+5
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* fpga: lib: Add more CtrlPort constantsWade Fife2020-08-191-7/+12
| | | | Add some missing CtrlPort signal widths to ctrlport.vh.
* fpga: lib: Add ctrlport_to_regport bridgeWade Fife2020-08-192-0/+91
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* fpga: rfnoc: Enable clean switch in SwitchboardWade Fife2020-08-131-1/+1
| | | | | This change prevents packets from being chopped midway if the switchboard configuration is changed when a packet is in flight.
* fpga: lib: Fix SWITCH_ON_LAST in axi_mux_selectWade Fife2020-08-131-18/+39
| | | | | Thange allows the mux to switch cleanly between packets, if the mux select input is changed while a packet is in flight.
* fpga: lib: add handshake to replace FIFO for ctrlport CDCMax Köhler2020-08-133-48/+143
| | | | | | | | The clock crossing of the ctrlport used FIFOs to transfer requests and responses between clock domains. This commit adds a handshake based on the pulse synchronizer to reduce the resource usage for ctrlport clock domain crossing. Data is stored in a single register while the pulse synchronizer handles the signaling of valid flags.
* fpga: rfnoc: Fix clock crossing in axis_data_to_chdrWade Fife2020-08-121-69/+89
| | | | | | | | | This fixes some incorrectly handled clock crossings from axis_data_clk to axis_chdr_clk, which could have manifested as timing failures (on E320) or incorrect behavior, depending on the product and noc_shell configuration. Also cleans up trailing white space.
* fpga: lib: Change max FFT size to 1024Wade Fife2020-08-111-2/+2
| | | | | | | | | | | | | The max FFT size was 4096, but we don't currently have any devices that can do that without modification. This is because, currently, the FFT size must be the same as the packet size, and the largest packet size supported by most devices is about 8000 bytes, or 2000 sc16 samples. Therefore, the largest FFT size supported without modifying other code is 1024 samples. This change frees up about 21% of the LUTs and 36% of the BRAM used by axi_fft and makes the software block controller and the IP agree on the maximum FFT size.
* fpga: rfnoc: Add tests to FFT blockWade Fife2020-08-102-39/+202
| | | | | This adds additional tests to the testbench to cover register reads and basic IFFT functionaltiy.
* fpga: lib: add Intel MAX10 architecture for 2clk FIFOMax Köhler2020-08-062-28/+33
| | | | | | | | | | | | | This commit derives parameters for MAX10 devices if provided by the DEVICE parameter. MAX10 devices FIFO generator support up to 36 bit wide FIFOs using embedded memory (M9K) in simple dual port mode, which is treated equally to RAM in the parameters. In combination with sorting the ctrlport signals by usage, the used resources can be reduced on the MAX10 devices from 6 to 3 M9K blocks for a ctrlport_clk_cross instance without time and portids.
* fpga: lib: Update xport_svAndrew Moch2020-08-056-182/+437
| | | | | | | | | - Detect dropped words at the dispatch level. This prevents an overflow on CHDR from block CPU. - Dropped packets are recorded as CPU or CHDR drop count - Refactor to put chdr_xport_adapter.sv in different clock domain to improve timing - Unwrinkle tkeep/trailing transitions
* fpga: rfnoc: Add RFNoC Keep One in N blockAaron Rossetto2020-08-057-0/+1432
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* fpga: rfnoc: Add RFNoC Replay blockWade Fife2020-08-0411-875/+4101
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* fpga: rfnoc: Add 4 KiB boundary check to sim_axi_ramWade Fife2020-08-041-0/+12
| | | | | Adding a check for bursts that cross the 4 KiB boundary to the AXI4 memory model. Crossing a 4 KiB boundary is not allowed by AXI4.
* fpga: rfnoc: Add support for CHDR_W < ITEM_W*NIPCWade Fife2020-08-042-137/+195
| | | | | | | | | This change fixes the case where CHDR_W < ITEM_W*NIPC. It also adds a state machine to stall the input to the pyld_fifo to ensure that the pkt_info_fifo will not overflow. Previously in some cases it allowed the same word to be inserted into the pyld_fifo multiple times.
* fpga: lib: Fix comments and indentation in axi_fifo_short.vWade Fife2020-08-041-98/+87
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* fpga: lib: Add xge features for new xport_svAndrew Moch2020-07-311-100/+191
| | | | | | | | | | - Made some things optional to reduce logic when used with the new xport_sv: (1) Clocking to sys_clk (2) Preamble insertion - New options to CUTTHROUGH faster on the TX path. The new xport_sv already has a gate to accumulate at its clock crossing.
* fpga: lib: Update AxiLiteIfAndrew Moch2020-07-311-1/+74
| | | | | This fixes a bug on wrstb in AxiLiteIf and adds a new AxiLiteIf_v that can be used to stitch onto Verilog port_maps.
* fpga: lib: Fix chdr_mgmt_pkt_handler when CHDR_W != 64Andrew Moch2020-07-301-1/+1
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* fpga: rfnoc: Add Signal Generator RFNoC blockWade Fife2020-07-3012-18/+1925
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* fpga: lib: Add axis_packetize moduleWade Fife2020-07-302-0/+162
| | | | | | This module takes an AXI-Stream without TLAST and outputs the same AXI-Stream with TLAST based on the provided packet size input.
* fpga: Add Switchboard RFNoC blockJesse Zhang2020-07-307-0/+1121
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* TwinRX: Fix increased noise floormichael-west2020-07-211-1/+1
| | | | | | - Fixed bus width from 25 to 24 bits Signed-off-by: michael-west <michael.west@ettus.com>
* fpga: remove liberioRobertWalstab2020-07-203-126/+2
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* fpga: rfnoc: Fix testbenches to run under ModelSimWade Fife2020-07-208-86/+64
| | | | | | This updates the makefiles for the testbenches so they can be run using "make modelsim" without any additional hacks. The "xsim" and "vsim" simulation targets also still work.
* fpga: rfnoc: Add RFNoC Moving Average blockWade Fife2020-07-168-0/+1587
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* fpga: lib: modify ctrlport decoder to Verilog 2001 compatible syntaxMax Köhler2020-07-101-39/+41
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* fpga: lib: Add width agnostic version of Ethernet InterfaceAndrew Moch2020-06-3013-0/+3339
| | | | | | | | | | | | | | | | | | The rnfoc/xport section is refactored in System Verilog to allow the following improvements (1) CPU_W - Sets the size of the c2e and e2c pipes. This can be run at a different clock rate than the main ethernet pipe (2) CHDR_W - Sets the size of the v2e and e2v pipes. This can be run at a different clock rate than the main ethernet pipe (3) ENET_W - Sets the size of the eth_tx and eth_rx pipes. eth_interface_tb runs traffic from e2c,e2v,v2e,c2e simultaneously against the original xport_sv implementation, and against the new implementation with widths of 64/128/512. A chdr_management node info request queries the port info of the node0 in the eth_interface. eth_ifc_synth_test.sv can be compiled with the make xsim target to test out the size of various configurations.
* fpga: rfnoc: Add Log-Power blockWade Fife2020-06-296-0/+1006
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* fpga: rfnoc: Fix chdr_update_length functionWade Fife2020-06-291-1/+1
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* fpga: rfnoc: Add RFNoC Window blockWade Fife2020-06-298-0/+1454
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* fpga: lib: Fix axi_packet_gate RAM dib widthWade Fife2020-06-291-1/+1
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* fpga: lib: Add features to axi_lite.vhAndrew Moch2020-06-261-23/+62
| | | | | | Contains a fix for the AXI4LITE_ASSIGN macro, and adds AXI4LITE_PORT_ASSIGN, AXI4LITE_PORT_ASSIGN_NR, and AXI4LITE_DEBUG_ASSIGN macros.
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