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* fpga: rfnoc: Add ability to disable output flow controlWade Fife2021-04-142-7/+22
* fpga: lib: Add rx_front_end_gen3 testbenchWade Fife2021-04-092-0/+247
* fpga: lib: Update round_sd to eliminate X from simulationWade Fife2021-04-091-14/+45
* fpga: lib: Fix simulation of axi_fir_filterWade Fife2021-04-091-1/+1
* TwinRX: Remove frontend filtermichael-west2021-04-081-59/+8
* fpga: docs: Improve documentation of rx_frontend_gen3Martin Braun2021-04-071-1/+73
* fpga: lib: Fix DDS_SIN_COS_LUT outputs in makefilePaul Butler2021-03-311-1/+1
* fpga: dsp: Fix formatting of rx_dcoffset and add docsMartin Braun2021-03-091-38/+110
* fpga: e320: Improve timing on LVDS interfaceWade Fife2020-12-113-355/+539
* fpga: lib: add glitch free mux moduleMax Köhler2020-12-032-0/+30
* fpga: lib: Fix axis_strm_monitor parametersWade Fife2020-10-201-2/+2
* fpga: lib: Fix small packets stuck in 10 GbE TXAndrew Moch2020-10-051-3/+17
* fpga: lib: Fix 10 GbE cut-through modeAndrew Moch2020-09-161-4/+16
* fpga: lib: add generic to disable bitq engine tri-statingMax Köhler2020-09-162-11/+16
* fpga: sim: chdr_stream_endpoint_tb improvementsWade Fife2020-08-312-36/+150
* fpga: rfnoc: Update CHDR stream INIT commandWade Fife2020-08-281-3/+10
* fpga: lib: Fix lint warningsWade Fife2020-08-283-3/+3
* fpga: rfnoc: Remove deprecated filesWade Fife2020-08-2322-2674/+5
* fpga: lib: Add more CtrlPort constantsWade Fife2020-08-191-7/+12
* fpga: lib: Add ctrlport_to_regport bridgeWade Fife2020-08-192-0/+91
* fpga: rfnoc: Enable clean switch in SwitchboardWade Fife2020-08-131-1/+1
* fpga: lib: Fix SWITCH_ON_LAST in axi_mux_selectWade Fife2020-08-131-18/+39
* fpga: lib: add handshake to replace FIFO for ctrlport CDCMax Köhler2020-08-133-48/+143
* fpga: rfnoc: Fix clock crossing in axis_data_to_chdrWade Fife2020-08-121-69/+89
* fpga: lib: Change max FFT size to 1024Wade Fife2020-08-111-2/+2
* fpga: rfnoc: Add tests to FFT blockWade Fife2020-08-102-39/+202
* fpga: lib: add Intel MAX10 architecture for 2clk FIFOMax Köhler2020-08-062-28/+33
* fpga: lib: Update xport_svAndrew Moch2020-08-056-182/+437
* fpga: rfnoc: Add RFNoC Keep One in N blockAaron Rossetto2020-08-057-0/+1432
* fpga: rfnoc: Add RFNoC Replay blockWade Fife2020-08-0411-875/+4101
* fpga: rfnoc: Add 4 KiB boundary check to sim_axi_ramWade Fife2020-08-041-0/+12
* fpga: rfnoc: Add support for CHDR_W < ITEM_W*NIPCWade Fife2020-08-042-137/+195
* fpga: lib: Fix comments and indentation in axi_fifo_short.vWade Fife2020-08-041-98/+87
* fpga: lib: Add xge features for new xport_svAndrew Moch2020-07-311-100/+191
* fpga: lib: Update AxiLiteIfAndrew Moch2020-07-311-1/+74
* fpga: lib: Fix chdr_mgmt_pkt_handler when CHDR_W != 64Andrew Moch2020-07-301-1/+1
* fpga: rfnoc: Add Signal Generator RFNoC blockWade Fife2020-07-3012-18/+1925
* fpga: lib: Add axis_packetize moduleWade Fife2020-07-302-0/+162
* fpga: Add Switchboard RFNoC blockJesse Zhang2020-07-307-0/+1121
* TwinRX: Fix increased noise floormichael-west2020-07-211-1/+1
* fpga: remove liberioRobertWalstab2020-07-203-126/+2
* fpga: rfnoc: Fix testbenches to run under ModelSimWade Fife2020-07-208-86/+64
* fpga: rfnoc: Add RFNoC Moving Average blockWade Fife2020-07-168-0/+1587
* fpga: lib: modify ctrlport decoder to Verilog 2001 compatible syntaxMax Köhler2020-07-101-39/+41
* fpga: lib: Add width agnostic version of Ethernet InterfaceAndrew Moch2020-06-3013-0/+3339
* fpga: rfnoc: Add Log-Power blockWade Fife2020-06-296-0/+1006
* fpga: rfnoc: Fix chdr_update_length functionWade Fife2020-06-291-1/+1
* fpga: rfnoc: Add RFNoC Window blockWade Fife2020-06-298-0/+1454
* fpga: lib: Fix axi_packet_gate RAM dib widthWade Fife2020-06-291-1/+1
* fpga: lib: Add features to axi_lite.vhAndrew Moch2020-06-261-23/+62
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