| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | fpga: e320: Improve timing on LVDS interface | Wade Fife | 2020-12-11 | 3 | -355/+539 |
| * | fpga: lib: add glitch free mux module | Max Köhler | 2020-12-03 | 2 | -0/+30 |
| * | fpga: lib: Fix axis_strm_monitor parameters | Wade Fife | 2020-10-20 | 1 | -2/+2 |
| * | fpga: lib: Fix small packets stuck in 10 GbE TX | Andrew Moch | 2020-10-05 | 1 | -3/+17 |
| * | fpga: lib: Fix 10 GbE cut-through mode | Andrew Moch | 2020-09-16 | 1 | -4/+16 |
| * | fpga: lib: add generic to disable bitq engine tri-stating | Max Köhler | 2020-09-16 | 2 | -11/+16 |
| * | fpga: sim: chdr_stream_endpoint_tb improvements | Wade Fife | 2020-08-31 | 2 | -36/+150 |
| * | fpga: rfnoc: Update CHDR stream INIT command | Wade Fife | 2020-08-28 | 1 | -3/+10 |
| * | fpga: lib: Fix lint warnings | Wade Fife | 2020-08-28 | 3 | -3/+3 |
| * | fpga: rfnoc: Remove deprecated files | Wade Fife | 2020-08-23 | 22 | -2674/+5 |
| * | fpga: lib: Add more CtrlPort constants | Wade Fife | 2020-08-19 | 1 | -7/+12 |
| * | fpga: lib: Add ctrlport_to_regport bridge | Wade Fife | 2020-08-19 | 2 | -0/+91 |
| * | fpga: rfnoc: Enable clean switch in Switchboard | Wade Fife | 2020-08-13 | 1 | -1/+1 |
| * | fpga: lib: Fix SWITCH_ON_LAST in axi_mux_select | Wade Fife | 2020-08-13 | 1 | -18/+39 |
| * | fpga: lib: add handshake to replace FIFO for ctrlport CDC | Max Köhler | 2020-08-13 | 3 | -48/+143 |
| * | fpga: rfnoc: Fix clock crossing in axis_data_to_chdr | Wade Fife | 2020-08-12 | 1 | -69/+89 |
| * | fpga: lib: Change max FFT size to 1024 | Wade Fife | 2020-08-11 | 1 | -2/+2 |
| * | fpga: rfnoc: Add tests to FFT block | Wade Fife | 2020-08-10 | 2 | -39/+202 |
| * | fpga: lib: add Intel MAX10 architecture for 2clk FIFO | Max Köhler | 2020-08-06 | 2 | -28/+33 |
| * | fpga: lib: Update xport_sv | Andrew Moch | 2020-08-05 | 6 | -182/+437 |
| * | fpga: rfnoc: Add RFNoC Keep One in N block | Aaron Rossetto | 2020-08-05 | 7 | -0/+1432 |
| * | fpga: rfnoc: Add RFNoC Replay block | Wade Fife | 2020-08-04 | 11 | -875/+4101 |
| * | fpga: rfnoc: Add 4 KiB boundary check to sim_axi_ram | Wade Fife | 2020-08-04 | 1 | -0/+12 |
| * | fpga: rfnoc: Add support for CHDR_W < ITEM_W*NIPC | Wade Fife | 2020-08-04 | 2 | -137/+195 |
| * | fpga: lib: Fix comments and indentation in axi_fifo_short.v | Wade Fife | 2020-08-04 | 1 | -98/+87 |
| * | fpga: lib: Add xge features for new xport_sv | Andrew Moch | 2020-07-31 | 1 | -100/+191 |
| * | fpga: lib: Update AxiLiteIf | Andrew Moch | 2020-07-31 | 1 | -1/+74 |
| * | fpga: lib: Fix chdr_mgmt_pkt_handler when CHDR_W != 64 | Andrew Moch | 2020-07-30 | 1 | -1/+1 |
| * | fpga: rfnoc: Add Signal Generator RFNoC block | Wade Fife | 2020-07-30 | 12 | -18/+1925 |
| * | fpga: lib: Add axis_packetize module | Wade Fife | 2020-07-30 | 2 | -0/+162 |
| * | fpga: Add Switchboard RFNoC block | Jesse Zhang | 2020-07-30 | 7 | -0/+1121 |
| * | TwinRX: Fix increased noise floor | michael-west | 2020-07-21 | 1 | -1/+1 |
| * | fpga: remove liberio | RobertWalstab | 2020-07-20 | 3 | -126/+2 |
| * | fpga: rfnoc: Fix testbenches to run under ModelSim | Wade Fife | 2020-07-20 | 8 | -86/+64 |
| * | fpga: rfnoc: Add RFNoC Moving Average block | Wade Fife | 2020-07-16 | 8 | -0/+1587 |
| * | fpga: lib: modify ctrlport decoder to Verilog 2001 compatible syntax | Max Köhler | 2020-07-10 | 1 | -39/+41 |
| * | fpga: lib: Add width agnostic version of Ethernet Interface | Andrew Moch | 2020-06-30 | 13 | -0/+3339 |
| * | fpga: rfnoc: Add Log-Power block | Wade Fife | 2020-06-29 | 6 | -0/+1006 |
| * | fpga: rfnoc: Fix chdr_update_length function | Wade Fife | 2020-06-29 | 1 | -1/+1 |
| * | fpga: rfnoc: Add RFNoC Window block | Wade Fife | 2020-06-29 | 8 | -0/+1454 |
| * | fpga: lib: Fix axi_packet_gate RAM dib width | Wade Fife | 2020-06-29 | 1 | -1/+1 |
| * | fpga: lib: Add features to axi_lite.vh | Andrew Moch | 2020-06-26 | 1 | -23/+62 |
| * | fpga: lib: Add synthesizable AXI4-Stream SV components | Andrew Moch | 2020-06-25 | 15 | -0/+3201 |
| * | fpga: rfnoc: Fix read suppression test in rfnoc_block_axi_ram_fifo_tb | Wade Fife | 2020-06-25 | 1 | -8/+16 |
| * | fpga: lib: Add interface and model for AXI4-Lite | Andrew Moch | 2020-06-24 | 4 | -0/+349 |
| * | fpga: lib: Pipeline and add clken to ip_hdr_checksum | Andrew Moch | 2020-06-24 | 4 | -66/+51 |
| * | fpga: rfnoc: Add support for 512-bit CHDR widths | Andrew Moch | 2020-06-18 | 16 | -220/+358 |
| * | fpga: lib: add extended spi core for 64bit | Max Köhler | 2020-06-17 | 2 | -0/+287 |
| * | fpga: lib: extend wb_spi ability to limit transmission length | Max Köhler | 2020-06-04 | 1 | -3/+9 |
| * | fpga: lib: Fix writes in axil_regport_master | Andrew Moch | 2020-06-04 | 1 | -23/+43 |
