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* rfnoc: Fix noc_shell direction commentsWade Fife2021-12-0818-81/+86
| | | | | | Some comments describing data flow direction were wrong. This commit updates the Mako files and updates the noc_shell modules with newly generated versions.
* fpga: Add ability to get time from Radio blockmichael-west2021-11-173-2/+26
| | | | | | Added registers to read back radio time. Bumped minor compat. Signed-off-by: michael-west <michael.west@ettus.com>
* siggen: Fix direction of rotationWade Fife2021-10-273-25/+28
| | | | | | | | | The I and Q were swapped in sine_tone, which caused confusion and made the rotation of REG_CARTESIAN clockwise by default. This effectively made the resulting frequency negative. This PR makes the I and Q order consistent with RFNoC and fixes the direction of rotation so that a positive value for REG_PHASE_INC (phase increment) results in a counter-clockwise rotation, which yields a positive frequency.
* fpga: Remove stale references to UHD_FPGA_DIRWade Fife2021-09-087-14/+7
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* rfnoc: duc: Remove stale references to CORDICWade Fife2021-08-081-18/+15
| | | | | Updated some comments that still referenced the old CORDIC implementation, which is no longer used.
* fpga: lib: Add rx_front_end_gen3 testbenchWade Fife2021-04-092-0/+247
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* TwinRX: Remove frontend filtermichael-west2021-04-081-59/+8
| | | | | | | | | | Removing the FIR filter in the frontend to reclaim resources and remove redundancy when using a DDC block. The default image has a DDC block, so only users making custom RFNoC images and using TwinRX will need to take care to properly downconvert the full bandwidth coming from the radio block. Signed-off-by: michael-west <michael.west@ettus.com>
* fpga: docs: Improve documentation of rx_frontend_gen3Martin Braun2021-04-071-1/+73
| | | | Also fixes a typo in the calibration manual page.
* fpga: rfnoc: Enable clean switch in SwitchboardWade Fife2020-08-131-1/+1
| | | | | This change prevents packets from being chopped midway if the switchboard configuration is changed when a packet is in flight.
* fpga: rfnoc: Add tests to FFT blockWade Fife2020-08-102-39/+202
| | | | | This adds additional tests to the testbench to cover register reads and basic IFFT functionaltiy.
* fpga: rfnoc: Add RFNoC Keep One in N blockAaron Rossetto2020-08-057-0/+1432
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* fpga: rfnoc: Add RFNoC Replay blockWade Fife2020-08-048-0/+4101
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* fpga: rfnoc: Add 4 KiB boundary check to sim_axi_ramWade Fife2020-08-041-0/+12
| | | | | Adding a check for bursts that cross the 4 KiB boundary to the AXI4 memory model. Crossing a 4 KiB boundary is not allowed by AXI4.
* fpga: rfnoc: Add Signal Generator RFNoC blockWade Fife2020-07-308-0/+1743
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* fpga: Add Switchboard RFNoC blockJesse Zhang2020-07-307-0/+1121
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* TwinRX: Fix increased noise floormichael-west2020-07-211-1/+1
| | | | | | - Fixed bus width from 25 to 24 bits Signed-off-by: michael-west <michael.west@ettus.com>
* fpga: rfnoc: Fix testbenches to run under ModelSimWade Fife2020-07-206-73/+51
| | | | | | This updates the makefiles for the testbenches so they can be run using "make modelsim" without any additional hacks. The "xsim" and "vsim" simulation targets also still work.
* fpga: rfnoc: Add RFNoC Moving Average blockWade Fife2020-07-168-0/+1587
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* fpga: rfnoc: Add Log-Power blockWade Fife2020-06-296-0/+1006
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* fpga: rfnoc: Add RFNoC Window blockWade Fife2020-06-298-0/+1454
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* fpga: rfnoc: Fix read suppression test in rfnoc_block_axi_ram_fifo_tbWade Fife2020-06-251-8/+16
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* fpga: rfnoc: Add support for 512-bit CHDR widthsAndrew Moch2020-06-185-74/+131
| | | | | | | | This fixes the rfnoc_null_src_sink, chdr_crossbar_nxn, and chdr_stream_endpoint blocks so that wider CHDR widths are properly supported. It also updates PkgChdrBfm to able to properly test these blocks. The testbenches have been updated to test both 64 and 512-bit widths.
* fpga: rfnoc: Add RFNoC Add/Sub blockWade Fife2020-05-286-0/+1183
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* rfnoc: Add Split Stream RFNoC blockWade Fife2020-05-286-0/+932
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* fpga: rfnoc: Add Vector IIR RFNoC blockWade Fife2020-05-196-0/+1376
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* fpga: rfnoc: Clean up ctrlport_splitter usageWade Fife2020-05-122-2/+2
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* TwinRX: Remove decimation from frontendMichael West2020-05-121-36/+52
| | | | | | | | | | | | | | The decimation in the rx_frontend_gen3 was added to reduce the bandwidth between the Radio and the DDC due to the limitation in bandwidth over the crossbar for dynamically connected blocks. The default FPGA image for the X300 now has a static connection between the Radio and DDC, so this is no longer necessary. This change allows the TwinRX receive channels to be time aligned with channels from other daughterboards so they can be used in the same streamer. Signed-off-by: Michael West <michael.west@ettus.com>
* DUC/DDC: Add variable time incrementMichael West2020-05-124-16/+23
| | | | | | | | | Sets time increment based on tick rate and sample rate instead of assuming one tick per sample. Defaults to legacy behavior. Minor compat number bumped on DUC and DDC blocks. Signed-off-by: Michael West <michael.west@ettus.com>
* fpga: Change default MTU to 10Wade Fife2020-05-112-2/+2
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* rfnoc: Add RFNoC fosphor blockWade Fife2020-04-146-0/+1584
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* sim: Add item support to RFNoC simulationWade Fife2020-03-096-6/+6
| | | | | This adds variants of the send and recv methods in RfnocBlockCtrlBfm and ChdrIfaceBfm that input/output items instead of CHDR words.
* sim: Parameterize chdr_word_t data typeWade Fife2020-03-097-8/+28
| | | | | | | | | | | | | | | | | | This replaces chdr_word_t, which was a statically defined 64-bit data type, with a paramaterizable data type that matches the defined CHDR_W. Code that formerly referenced the chdr_word_t data type can now define the data type for their desired CHDR_W and ITEM_W as follows: // Define the CHDR word and item/sample data types typedef ChdrData #(CHDR_W, ITEM_W)::chdr_word_t chdr_word_t; typedef ChdrData #(CHDR_W, ITEM_W)::item_t item_t; ITEM_W is optional when defining chdr_word_t if items are not needed. Static methods in the ChdrData class also provide the ability to convert between CHDR words and data items. For example: // Convert CHDR data buffer to a buffer of samples samples = ChdrData#(CHDR_W, ITEM_W)::chdr_to_item(data);
* rfnoc: Fix FIR and AXI RAM block register documentationWade Fife2020-03-052-9/+11
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* radio: Update TB to use new block ctrl connectWade Fife2020-02-191-41/+17
| | | | | This eliminates the complicated semaphore from the testbench and brings the radio testbench in line with the other testbenches.
* rfnoc: Update blocks to use autogenerated noc_shellWade Fife2020-02-0623-1825/+2407
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* Merge FPGA repository back into UHD repositoryMartin Braun2020-01-2853-0/+14730
The FPGA codebase was removed from the UHD repository in 2014 to reduce the size of the repository. However, over the last half-decade, the split between the repositories has proven more burdensome than it has been helpful. By merging the FPGA code back, it will be possible to create atomic commits that touch both FPGA and UHD codebases. Continuous integration testing is also simplified by merging the repositories, because it was previously difficult to automatically derive the correct UHD branch when testing a feature branch on the FPGA repository. This commit also updates the license files and paths therein. We are therefore merging the repositories again. Future development for FPGA code will happen in the same repository as the UHD host code and MPM code. == Original Codebase and Rebasing == The original FPGA repository will be hosted for the foreseeable future at its original local location: https://github.com/EttusResearch/fpga/ It can be used for bisecting, reference, and a more detailed history. The final commit from said repository to be merged here is 05003794e2da61cabf64dd278c45685a7abad7ec. This commit is tagged as v4.0.0.0-pre-uhd-merge. If you have changes in the FPGA repository that you want to rebase onto the UHD repository, simply run the following commands: - Create a directory to store patches (this should be an empty directory): mkdir ~/patches - Now make sure that your FPGA codebase is based on the same state as the code that was merged: cd src/fpga # Or wherever your FPGA code is stored git rebase v4.0.0.0-pre-uhd-merge Note: The rebase command may look slightly different depending on what exactly you're trying to rebase. - Create a patch set for your changes versus v4.0.0.0-pre-uhd-merge: git format-patch v4.0.0.0-pre-uhd-merge -o ~/patches Note: Make sure that only patches are stored in your output directory. It should otherwise be empty. Make sure that you picked the correct range of commits, and only commits you wanted to rebase were exported as patch files. - Go to the UHD repository and apply the patches: cd src/uhd # Or wherever your UHD repository is stored git am --directory fpga ~/patches/* rm -rf ~/patches # This is for cleanup == Contributors == The following people have contributed mainly to these files (this list is not complete): Co-authored-by: Alex Williams <alex.williams@ni.com> Co-authored-by: Andrej Rode <andrej.rode@ettus.com> Co-authored-by: Ashish Chaudhari <ashish@ettus.com> Co-authored-by: Ben Hilburn <ben.hilburn@ettus.com> Co-authored-by: Ciro Nishiguchi <ciro.nishiguchi@ni.com> Co-authored-by: Daniel Jepson <daniel.jepson@ni.com> Co-authored-by: Derek Kozel <derek.kozel@ettus.com> Co-authored-by: EJ Kreinar <ej@he360.com> Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com> Co-authored-by: Ian Buckley <ian.buckley@gmail.com> Co-authored-by: Jörg Hofrichter <joerg.hofrichter@ni.com> Co-authored-by: Jon Kiser <jon.kiser@ni.com> Co-authored-by: Josh Blum <josh@joshknows.com> Co-authored-by: Jonathon Pendlum <jonathan.pendlum@ettus.com> Co-authored-by: Martin Braun <martin.braun@ettus.com> Co-authored-by: Matt Ettus <matt@ettus.com> Co-authored-by: Michael West <michael.west@ettus.com> Co-authored-by: Moritz Fischer <moritz.fischer@ettus.com> Co-authored-by: Nick Foster <nick@ettus.com> Co-authored-by: Nicolas Cuervo <nicolas.cuervo@ettus.com> Co-authored-by: Paul Butler <paul.butler@ni.com> Co-authored-by: Paul David <paul.david@ettus.com> Co-authored-by: Ryan Marlow <ryan.marlow@ettus.com> Co-authored-by: Sugandha Gupta <sugandha.gupta@ettus.com> Co-authored-by: Sylvain Munaut <tnt@246tNt.com> Co-authored-by: Trung Tran <trung.tran@ettus.com> Co-authored-by: Vidush Vishwanath <vidush.vishwanath@ettus.com> Co-authored-by: Wade Fife <wade.fife@ettus.com>
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