uhd - Ettus' UHD Repository

	Commit message (Collapse)	Author	Age	Files	Lines
*	fpga: lib: Minor cleanup of axi_lite.vh	Lars Amsel	2021-06-03	1	-2/+23
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*	fpga: lib: Update AxiLiteIf	Andrew Moch	2020-07-31	1	-1/+74
\| \| \| \| \|	This fixes a bug on wrstb in AxiLiteIf and adds a new AxiLiteIf_v that can be used to stitch onto Verilog port_maps.
*	fpga: lib: Add features to axi_lite.vh	Andrew Moch	2020-06-26	1	-23/+62
\| \| \| \| \| \|	Contains a fix for the AXI4LITE_ASSIGN macro, and adds AXI4LITE_PORT_ASSIGN, AXI4LITE_PORT_ASSIGN_NR, and AXI4LITE_DEBUG_ASSIGN macros.
*	fpga: lib: Add interface and model for AXI4-Lite	Andrew Moch	2020-06-24	4	-0/+349
	(1) Synthesizable AxiLiteIf (2) Simulation model for AxiLite contains an AxiLiteTransaction class and an AxiLiteBfm class. Important Methods a. wr - performs non-blocking write and checks for expected response b. wr_block - performs a blocking write and provides response c. rd - performs a non-blocking read and checks for expected response d. rd_block - persforms a blocking read and provides response The model allows parallel execution of reads and writes, but enforces rd and write ordering when using the above methods. When transactions are posted directly, ordering is not guaranteed, and reads and writes are put on the interface immediately.