| Commit message (Collapse) | Author | Age | Files | Lines |
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The fuses weren't written correctly before, as we were
lacking parameters to avrdude.
Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
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- B2x0: FW compat number (goes with previous firmware update)
- X3x0: Max HW rev number
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Conflicts:
fpga-src
host/CMakeLists.txt
host/cmake/Modules/UHDVersion.cmake
host/lib/usrp/b200/b200_impl.hpp
host/lib/usrp/e300/e300_fpga_defs.hpp
host/lib/usrp/x300/x300_fw_common.h
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Note: This firmware does *not* support Rev B units.
Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
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- Logging in conjunction with B200 side-channel utility
(using UART or directly over USB)
- More and better configurability, e.g. Tx voltage swing
and DMA configuration
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* Bumped compatibility version to 3
* firmware: Ethernet, clkdist bugfixes
* lib: fixed invalid rev detection
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Conflicts:
host/lib/usrp/b200/b200_impl.cpp
host/lib/usrp/b200/b200_impl.hpp
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Conflicts:
firmware/fx3/b200/b200_usb_descriptors.c
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Conflicts:
firmware/fx3/README.md
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- Refactored SFP+ hotplug handler
- GigE link state comes from SFP+ status and PHY status
- Multiple tracing enhancements
- Bumped firmware compat number to 4
- Bumpled FPGA compat number to 10
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* Fixed Ethernet initialization problem
* Improved external reference detection
* Added gratuitous ARP, sent upon power-up
* Tweaked host-side timing for initialization and firmware burning
* Fixed logic for dealing with firmware incompatibility
* Misc efficiency/reliability improvements to firmware's network code
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- FX3 does not respond to AD9361 firmware transaction VREQs
- FX3 does not respond to AD9361 SPI transaction VREQs
- Deleted all AD9361 firmware files
- Bumped FW compat to 6
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- Fix for BUG #485: B200: Channels Swap Between Runs
# Added code to transition state machine out of FDD while reconfiguring active chains.
# bb:0b9929 Mon Jun 16 14:56:26 2014 -0700
- Fix for BUG #500: B210: RX channels are not phase aligned
# Set bit to invert RX if internal LNA is bypassed
# bb:0a4565 Thu Jun 5 17:10:37 2014 -0700
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- Switched to FPGA SPI engine
- Moved firmware AD9361 driver to UHD
- Bumped FW compat to 5, FPGA compat to 4
- Known Issue: AD9361 SPI rate is too slow
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* OctoClock can communicate with UHD over Ethernet
* Can read NMEA strings from GPSDO and send to host
* Added multi_usrp_clock class for clock devices
* uhd::device can now filter to return only USRP devices or clock devices
* New OctoClock bootloader can accept firmware download over Ethernet
* Added octoclock_burn_eeprom,octoclock_firmware_burner utilities
* Added test_clock_synch example to show clock API
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- Corrected types of some variables to be boost types.
- Removed debugging code accidentally left in.
- Changed some compiled out error messages to log messages.
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made in a random wait iterative fashion
Fix for BUG #460: X300: GPGGA sensor most often empty, while RMC is usually OK
- Added checksum verification of NMEA strings
- Improved handling of short or malformed strings
- Fixed GPSDO data synchronization between X300 firmware and host
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- Disabled all packet forwarding
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- Restored link state handling.
- Enabled forwarding of packets not addressed to this device's MAC address.
- Kept forwarding of broadcast packets disabled.
NOTE: This is a workaround and not a permanent fix.
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- Disabled packet forwarding and link state cycle detection in firmware.
- Fixed the link state algorithm so the updating runs the first time and
the forwading update only happens when necessary.
- Added check for 10GbE before calling MDIO functions.
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Reverting "x300: ICMP_DUR handler fixed. Supposedly closes #256."
This reverts commit 69317629f353734d5ac21dc78be105b2f0164497.
Resolved Conflicts:
firmware/x300/x300/x300_main.c
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When an ICMP dest unreachable pkt arrives,
the fw needs to know how to shutoff the DSP.
This offset for the reset register was
broken by a previous fix for register overlap.
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