| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | b200: AD9361 firmware bugfixes | Ashish Chaudhari | 2014-08-01 | 1 | -0/+19 |
| | | | | | | | | | | | - Fix for BUG #485: B200: Channels Swap Between Runs # Added code to transition state machine out of FDD while reconfiguring active chains. # bb:0b9929 Mon Jun 16 14:56:26 2014 -0700 - Fix for BUG #500: B210: RX channels are not phase aligned # Set bit to invert RX if internal LNA is bypassed # bb:0a4565 Thu Jun 5 17:10:37 2014 -0700 | ||||
| * | b200: Moved AD9361 driver to host | Ashish Chaudhari | 2014-08-01 | 4 | -11/+17 |
| | | | | | | | | - Switched to FPGA SPI engine - Moved firmware AD9361 driver to UHD - Bumped FW compat to 5, FPGA compat to 4 - Known Issue: AD9361 SPI rate is too slow | ||||
| * | b2xx: Pulling FX3 and AD9361 source code into master. | Ben Hilburn | 2014-04-07 | 23 | -0/+7279 |
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| Ettus' UHD Repository |
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