| Commit message (Collapse) | Author | Age | Files | Lines |
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- B2x0: FW compat number (goes with previous firmware update)
- X3x0: Max HW rev number
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- Logging in conjunction with B200 side-channel utility
(using UART or directly over USB)
- More and better configurability, e.g. Tx voltage swing
and DMA configuration
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Conflicts:
firmware/fx3/b200/b200_usb_descriptors.c
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Conflicts:
firmware/fx3/README.md
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- FX3 does not respond to AD9361 firmware transaction VREQs
- FX3 does not respond to AD9361 SPI transaction VREQs
- Deleted all AD9361 firmware files
- Bumped FW compat to 6
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- Fix for BUG #485: B200: Channels Swap Between Runs
# Added code to transition state machine out of FDD while reconfiguring active chains.
# bb:0b9929 Mon Jun 16 14:56:26 2014 -0700
- Fix for BUG #500: B210: RX channels are not phase aligned
# Set bit to invert RX if internal LNA is bypassed
# bb:0a4565 Thu Jun 5 17:10:37 2014 -0700
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- Switched to FPGA SPI engine
- Moved firmware AD9361 driver to UHD
- Bumped FW compat to 5, FPGA compat to 4
- Known Issue: AD9361 SPI rate is too slow
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