aboutsummaryrefslogtreecommitdiffstats
path: root/firmware/fx3
Commit message (Collapse)AuthorAgeFilesLines
* Definitions of MASK_GPIO_SHDN_SW and GPIO_AUX_PWR_ON Errorsfenggnef2018-08-011-2/+2
| | | | | MASK_GPIO_SHDN_SW ( GPIO[52] ) should be shifted by "GPIO_SHDN_SW" but "GPIO_FX3_SCLK ". Otherwise GPIOs of FX3 will initial GPIO_FX3_SCLK ( GPIO[53] ) as GPIO and SPI respectively. It will make GPIO[53] conflict between SPI and GPIO, and SHDN_SW will not work properly as a power switch.
* b200: fw: Change USB2 Buffer Size and Buffer CountMartin Braun2018-07-121-2/+2
| | | | | | Change FX3 firmware for USB2 so the eob flag is always seen, particularly on packets that are a multiple of 512 bytes in size.
* Merge branch 'maint'Martin Braun2017-03-241-1/+1
|\
| * Docs: Updated FX3 SDK link in readmeDerek Kozel2017-03-211-1/+1
| |
* | B200: FX3 performance optimizations based on Cypress AN86947michael-west2017-01-202-6/+6
|/
* Updated compat numbers for B2x0 and X3x0Martin Braun2015-07-141-1/+1
| | | | | - B2x0: FW compat number (goes with previous firmware update) - X3x0: Max HW rev number
* fx3: New firmware features: Logging, more configurationBalint Seeber2015-07-143-364/+756
| | | | | | | - Logging in conjunction with B200 side-channel utility (using UART or directly over USB) - More and better configurability, e.g. Tx voltage swing and DMA configuration
* FX3: Updating FW to support NI-USRP VID and PIDsBen Hilburn2015-04-153-3/+120
| | | | | Conflicts: firmware/fx3/b200/b200_usb_descriptors.c
* FX3: Updating FX3 FW build docsBen Hilburn2015-04-151-5/+5
| | | | | Conflicts: firmware/fx3/README.md
* b200: Bumped FX3 firmware compat number to 7.Ashish Chaudhari2014-10-011-1/+1
|
* docs: Added a note on FX3 SDK versionMartin Braun2014-10-011-0/+1
|
* b200: Removed all AD9361 related firmwareAshish Chaudhari2014-08-1212-2746/+5
| | | | | | | - FX3 does not respond to AD9361 firmware transaction VREQs - FX3 does not respond to AD9361 SPI transaction VREQs - Deleted all AD9361 firmware files - Bumped FW compat to 6
* b200: AD9361 firmware bugfixesAshish Chaudhari2014-08-011-0/+19
| | | | | | | | | | - Fix for BUG #485: B200: Channels Swap Between Runs # Added code to transition state machine out of FDD while reconfiguring active chains. # bb:0b9929 Mon Jun 16 14:56:26 2014 -0700 - Fix for BUG #500: B210: RX channels are not phase aligned # Set bit to invert RX if internal LNA is bypassed # bb:0a4565 Thu Jun 5 17:10:37 2014 -0700
* b200: Moved AD9361 driver to hostAshish Chaudhari2014-08-014-11/+17
| | | | | | | - Switched to FPGA SPI engine - Moved firmware AD9361 driver to UHD - Bumped FW compat to 5, FPGA compat to 4 - Known Issue: AD9361 SPI rate is too slow
* b2xx: Pulling FX3 and AD9361 source code into master.Ben Hilburn2014-04-0723-0/+7279
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-27 08:22:59 +0000