uhd - Ettus' UHD Repository

	Commit message (Collapse)	Author	Age	Files	Lines
*	Definitions of MASK_GPIO_SHDN_SW and GPIO_AUX_PWR_ON Errors	fenggnef	2018-08-01	1	-2/+2
\| \| \| \| \|	MASK_GPIO_SHDN_SW ( GPIO[52] ) should be shifted by "GPIO_SHDN_SW" but "GPIO_FX3_SCLK ". Otherwise GPIOs of FX3 will initial GPIO_FX3_SCLK ( GPIO[53] ) as GPIO and SPI respectively. It will make GPIO[53] conflict between SPI and GPIO, and SHDN_SW will not work properly as a power switch.
*	b200: fw: Change USB2 Buffer Size and Buffer Count	Martin Braun	2018-07-12	1	-2/+2
\| \| \| \| \| \|	Change FX3 firmware for USB2 so the eob flag is always seen, particularly on packets that are a multiple of 512 bytes in size.
*	Merge branch 'maint'	Martin Braun	2017-03-24	1	-1/+1
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\| *	Docs: Updated FX3 SDK link in readme	Derek Kozel	2017-03-21	1	-1/+1
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* \|	B200: FX3 performance optimizations based on Cypress AN86947	michael-west	2017-01-20	2	-6/+6
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*	Updated compat numbers for B2x0 and X3x0	Martin Braun	2015-07-14	1	-1/+1
\| \| \| \| \|	- B2x0: FW compat number (goes with previous firmware update) - X3x0: Max HW rev number
*	fx3: New firmware features: Logging, more configuration	Balint Seeber	2015-07-14	3	-364/+756
\| \| \| \| \| \| \|	- Logging in conjunction with B200 side-channel utility (using UART or directly over USB) - More and better configurability, e.g. Tx voltage swing and DMA configuration
*	FX3: Updating FW to support NI-USRP VID and PIDs	Ben Hilburn	2015-04-15	3	-3/+120
\| \| \| \| \|	Conflicts: firmware/fx3/b200/b200_usb_descriptors.c
*	FX3: Updating FX3 FW build docs	Ben Hilburn	2015-04-15	1	-5/+5
\| \| \| \| \|	Conflicts: firmware/fx3/README.md
*	b200: Bumped FX3 firmware compat number to 7.	Ashish Chaudhari	2014-10-01	1	-1/+1
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*	docs: Added a note on FX3 SDK version	Martin Braun	2014-10-01	1	-0/+1
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*	b200: Removed all AD9361 related firmware	Ashish Chaudhari	2014-08-12	12	-2746/+5
\| \| \| \| \| \| \|	- FX3 does not respond to AD9361 firmware transaction VREQs - FX3 does not respond to AD9361 SPI transaction VREQs - Deleted all AD9361 firmware files - Bumped FW compat to 6
*	b200: AD9361 firmware bugfixes	Ashish Chaudhari	2014-08-01	1	-0/+19
\| \| \| \| \| \| \| \| \| \|	- Fix for BUG #485: B200: Channels Swap Between Runs # Added code to transition state machine out of FDD while reconfiguring active chains. # bb:0b9929 Mon Jun 16 14:56:26 2014 -0700 - Fix for BUG #500: B210: RX channels are not phase aligned # Set bit to invert RX if internal LNA is bypassed # bb:0a4565 Thu Jun 5 17:10:37 2014 -0700
*	b200: Moved AD9361 driver to host	Ashish Chaudhari	2014-08-01	4	-11/+17
\| \| \| \| \| \| \|	- Switched to FPGA SPI engine - Moved firmware AD9361 driver to UHD - Bumped FW compat to 5, FPGA compat to 4 - Known Issue: AD9361 SPI rate is too slow
*	b2xx: Pulling FX3 and AD9361 source code into master.	Ben Hilburn	2014-04-07	23	-0/+7279