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* b200: fw: Change USB2 Buffer Size and Buffer CountMartin Braun2018-07-121-2/+2
| | | | | | Change FX3 firmware for USB2 so the eob flag is always seen, particularly on packets that are a multiple of 512 bytes in size.
* B200: FX3 performance optimizations based on Cypress AN86947michael-west2017-01-202-6/+6
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* Updated compat numbers for B2x0 and X3x0Martin Braun2015-07-141-1/+1
| | | | | - B2x0: FW compat number (goes with previous firmware update) - X3x0: Max HW rev number
* fx3: New firmware features: Logging, more configurationBalint Seeber2015-07-143-364/+756
| | | | | | | - Logging in conjunction with B200 side-channel utility (using UART or directly over USB) - More and better configurability, e.g. Tx voltage swing and DMA configuration
* FX3: Updating FW to support NI-USRP VID and PIDsBen Hilburn2015-04-153-3/+120
| | | | | Conflicts: firmware/fx3/b200/b200_usb_descriptors.c
* b200: Bumped FX3 firmware compat number to 7.Ashish Chaudhari2014-10-011-1/+1
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* b200: Removed all AD9361 related firmwareAshish Chaudhari2014-08-125-418/+3
| | | | | | | - FX3 does not respond to AD9361 firmware transaction VREQs - FX3 does not respond to AD9361 SPI transaction VREQs - Deleted all AD9361 firmware files - Bumped FW compat to 6
* b200: Moved AD9361 driver to hostAshish Chaudhari2014-08-011-1/+1
| | | | | | | - Switched to FPGA SPI engine - Moved firmware AD9361 driver to UHD - Bumped FW compat to 5, FPGA compat to 4 - Known Issue: AD9361 SPI rate is too slow
* b2xx: Pulling FX3 and AD9361 source code into master.Ben Hilburn2014-04-0711-0/+4318