aboutsummaryrefslogtreecommitdiffstats
Commit message (Collapse)AuthorAgeFilesLines
* usrp: work on meeting timing constraintsJosh Blum2012-04-105-25/+30
| | | | | | * fifo ctrl register the vita ticks and use late * vita de/framer make nchans const since we dont change it * simplify readback muxes to minimal usage
* Merge branch 'master' into nextJosh Blum2012-04-095-7/+67
|\ | | | | | | | | | | Conflicts: usrp2/top/N2x0/u2plus_core.v usrp2/top/USRP2/u2_core.v
| * Merge branch 'maint'Josh Blum2012-04-095-6/+6
| |\
| | * vita: moved clear register to overlap with nchan registerJosh Blum2012-04-095-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This fixes the bug where setting the format clears the vita RX. This is only an issue when the noclear option is set by UHD, because the format register is always so, so it always clears. Note: noclear is there to support the backwards compat API (pre streamer). Now, numchans and clear overlap. This is ok because in the host code, clear and numchans are always used together. All timing meets on N2xx and USRP2.
| * | Merge branch 'maint'Josh Blum2012-04-022-5/+5
| |\|
| | * b100: fix slave fifo data xfer exit conditionJosh Blum2012-04-012-5/+5
| | | | | | | | | | | | | | | | | | | | | When exiting the read/write data state, when the transfer count maxes out/peaks, the fifo read/write signals were getting this condition the cycle after with the state change.
| * | fpga: extract usage summary from map fileJosh Blum2012-03-271-0/+60
| |/
* | Merge branch 'master' into nextJosh Blum2012-03-264-85/+92
|\|
| * B100: port cleanups from b100-txbug to this branchNick Foster2012-03-262-28/+21
| |
| * fpga: fifo_2clock handles widths and sizes in-between corgensJosh Blum2012-03-251-21/+23
| |
| * b100: cleanup redundant logic for slwr and slrdJosh Blum2012-03-251-2/+2
| |
| * b100: extra data pktend cycle for fifo addrJosh Blum2012-03-251-2/+8
| |
| * b100: slave fifo fix for dst/src ready signalsJosh Blum2012-03-242-35/+41
| | | | | | | | | | | | | | | | Some of the changes my be overkill, but the idea is to be more careful about allowing FIFO IO to occur on transitions. The cal app was able to complete successfully.
* | spi core: ready logic low one cycle earlierJosh Blum2012-03-161-1/+1
| | | | | | | | | | | | | | FIFO ctrl can poke registers every other cycle, the extra time to register not ready for spi core was too long. And it with ~trigger to get the not-ready one cycle earlier, so FIFO ctrl can block on the 2nd potential spi transaction.
* | fifo ctrl: parameterize having a proto headerJosh Blum2012-03-164-10/+12
| |
* | fifo ctrl: rename fifo ctrl module and add sid ack paramJosh Blum2012-03-164-37/+40
| |
* | fifo ctrl: minor fixes for spi core, swap time defineJosh Blum2012-03-165-10/+10
| |
* | fifo ctrl: simplified perfs, added spi clock idle phaseJosh Blum2012-03-165-333/+341
| |
* | fifo ctrl: minor fixes from last commitJosh Blum2012-03-163-366/+366
| |
* | fifo ctrl: spi core work, fifo ctrl perifs, usrp2 supportJosh Blum2012-03-165-370/+429
| | | | | | | | | | | | | | | | Continued work on simple spi core. Added peripherals input to fifo ctrl so perifs can backpressure fifo ctrl. Copied the implementation into usrp2 core.
* | spi: created simple spi core (sr based)Josh Blum2012-03-164-383/+593
| |
* | fifo ctrl: simplified result packets (no tsf or sid)Josh Blum2012-03-161-16/+7
| |
* | fifo_ctrl: switched to medfifo and separate result fifoJosh Blum2012-03-163-92/+122
| |
* | fifo_ctrl: clear settings reg, and flow controlJosh Blum2012-03-163-10/+17
| |
* | fifo ctrl: added time compare for timed commandsJosh Blum2012-03-161-3/+7
| |
* | srb: created command queue, in and out state machinesJosh Blum2012-03-163-99/+162
| |
* | usrp2: added vrt pack/unpacker to fifo ctrlJosh Blum2012-03-161-40/+107
| |
* | usrp2: first pass implementation of fifo controlJosh Blum2012-03-166-10/+594
|/
* fpga: force -include_global for custom sourcesJosh Blum2012-03-129-13/+16
| | | | | | | | ISE will not recognize custom sources as part of the hierarchy, and thus will not compile (unless its the first macro...). Remove custom sources from the source list, and specially add them with the -include_global option.
* fpga: fix custom defs in some top level makefilesJosh Blum2012-03-084-101/+3
|
* usrp2/nseries: added churn to meet timingJosh Blum2012-02-182-2/+4
| | | | | Added churn to readback mux on nseries to make n200r4 meet timing. Also added churn to usrp2 for parallelism, but assigned to zero.
* vita rx: trigger clear after packet tranferJosh Blum2012-02-181-2/+22
| | | | | | | To avoid blocking conditions down the pipe, avoid clearing vita rx during packet transfer. Adds state machine to delay the clear until after xfer completes.
* dsp rework: fix dspengine_8to16 to handle padded packetsJosh Blum2012-02-171-4/+3
|
* dsp_engine: fix for upper/lower swap, and odd length packetsMatt Ettus2012-02-161-16/+20
|
* dsp rework: added flusher to vita tx chain on clearJosh Blum2012-02-151-8/+16
|
* dsp rework: minor simplification in vita_tx_deframerJosh Blum2012-02-131-4/+1
| | | | all n-series devices meet timing
* dsp rework: full-rate pipelining in vita tx deframerJosh Blum2012-02-121-37/+51
| | | | | | | | The vita tx deframer can now pass payload at clock rate. This enables TX streaming at interpolations factors of 2. The vector capabilities of TX deframer have been kept in-tact, and should be functional, however, only MAXCHAN=1 has been tested.
* dsp rework: pass enables into glue, update power trig, parameterize, fix ↵Josh Blum2012-02-109-103/+145
| | | | | | | | | | | | module inc DSP enables now pass through the glue and custom modules so it can be user-controlled. Updated power trigger to current spec, and added comments Pass width from dsp into glue, and use width to parameterize wires Fix custom module includes so they will build
* dsp rework: implement 64 bit ticks no secondsJosh Blum2012-02-0610-111/+57
|
* B100: External FPGA reset from FX2 reuses fpga_cfg_cclk.Nick Foster2012-02-062-2/+6
|
* dsp rework: pass vita clears into dsp modules, unified fifo clearsJosh Blum2012-02-0414-81/+76
|
* b100: timing constraints on GPIF linesJosh Blum2012-02-041-0/+9
|
* b100: connect all clears for gpifJosh Blum2012-02-033-15/+8
|
* power_trig: test code for power triggerMatt Ettus2012-02-021-0/+71
|
* dsp rework: rehash of the custom module stuff and readmeJosh Blum2012-02-0226-262/+544
|
* power_trig: first cut at power trigger with fixed delayMatt Ettus2012-02-022-2/+115
|
* dsp_rework: testbench enhancementsMatt Ettus2012-02-021-11/+34
|
* dsp rework: custom engine module for rx/tx vita chainJosh Blum2012-02-0113-138/+294
|
* dsp rework: register the sample in vita tx ctrlJosh Blum2012-02-011-2/+11
|
* Merge branch 'slave_fifo_rebase' into dsp_reworkJosh Blum2012-02-016-35/+509
|\ | | | | | | | | Conflicts: usrp2/top/B100/u1plus_core.v
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-16 03:25:59 +0000