| Commit message (Collapse) | Author | Age | Files | Lines |
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READ operations that can be in the extfifo pipeline.
Regenerated fifo_xlnx_512x36_2clk_18to36 to include prog_full output triggered at 1017 so that there are 6 empty spaces to accept
in flight read data upon completion.
Had to generate the FIFO using Coregen from ISE12.1 due to 10.1 verion not working correctly in FPGA
Still have to tackle making this simulate in Icarus
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current head UHD code.
Apparently operation is "flawless" but more regression and corner case regression could and should be done.
Tristate drivers have been added at the top level of the hierarchy for the SRAM databus as is considered good
practice for both Xilinx and ASIC design flows and so both top level and core fils have been touched.
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Loopback is running via the external ZBT SRAM...HOWEVER, its not running well, its stable but the data is corrupted sometimes.
Not clear if its a logic or AC timing/SI issue yet.
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and u2p
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* u1e: (130 commits)
invert led signals because they are active low
duh
allow for CS to rise before, at the same time, or after OE
better debug pins
watch the ethernet chip select on our debug bus
fix timing issue on DAC outputs with rev 2. This puts the whole system on a 90 degree phase shift
send all gpmc signals to mictor
updated pins to match rev2, removed dip switch, etc. seems to compile ok.
pins are different on rev2
fixed makefile to compile with our new system
add register to tell host about compatibility level and which image we are using
move declaration to make loopback compile
no need for protocol headers since we're not doing ethernet
match the signal names in this design
debug pins cleanup
properly integrate the new tx chain
catch up with tx_policy
attach run_tx and run_rx to leds
connect atr
delay the q channel to make the channels line up on the AD9862
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Conflicts:
usrp2/control_lib/Makefile.srcs
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asserted. which is the point of a CE, but... it works.
Also committed latest bootloader, might not be final version.
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adc signals from old adc on U2
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* tx_policy: (21 commits)
clean up DAC inversion and swapping to match schematics
Clean up iq swapping on RX. It is now swapped in the top level. widened muxes to 4 bits to match tx side and handle more ADCs in future
rx error context packets should not be marked as errors in the fifo
added compat number to usrp2 readback mux
makefile dependency fix for second expansion
provide a way to get out of the error state without processor intervention
sequence number reset upon programming streamid
attempt at avoiding infinite error messages
implemented "next packet" and "next burst" policies
sequence errors can happen on start of burst as well.
more informative error codes
cleaner error handling
introduce new error types
test mux and gen_context_pkt
this is an output file, it shouldn't be checked in
insert protocol engine flags when requested
move the streamid so it isn't at the same address as clear_state
connect the demux
fix a typo
tx error packets now muxed into the ethernet stream back to the host
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The script just looks for input/inout/outputs that are declared in the .v but not in the .ucf. If it finds an occurrence, it aborts the compile.
Removed pin "POR" from u2plus.v due to the script. Also reverted an error I introduced to test the script, which I mistakenly committed earlier.
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Changed debug pins to debug ICAP instead of VITA -- which makes it actually meet timing, too. Bonus.
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Normally high, goes low when pushed
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* ise12:
move declaration ahead of use
put run_tx and run_rx on the displayed LEDs
remove warnings
add mux and demux to build
mux multiple fifo streams into one. Allows priority or round robin
split fifo into 2 streams based on first line in each packet
fix to stop endless error packets
updated tests to match new features
error packets are now valid Extension Context packets error packets don't have a trailer any more streamid is now optional on data packets, set by header register trailer now has a bit to indicate successful End-of-burst hard-coded some header bits to correct values to ensure valid packets
reload bit for vita rx ctrl
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has already incremented by the time the data is returned
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