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| * | | Merge branch 'master' of ettus.sourcerepo.com:ettus/fpga into uhd_masterJosh Blum2010-06-15268-901/+1835
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| | * | new make works on ise12Matt Ettus2010-06-141-1/+7
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| | * | produces good bin filesMatt Ettus2010-06-114-57/+31
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| | * | first attempt at cleaning up the build systemMatt Ettus2010-06-1038-422/+583
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| | * | get rid of debug stuff to help timingMatt Ettus2010-06-081-7/+16
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| | * | move u2_core into u2_rev3 directory to simplify directory structure and save ↵Matt Ettus2010-06-085-46/+2
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| | * | allow other clock rates in vita timeMatt Ettus2010-06-081-13/+15
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| | * | report ise version in buildMatt Ettus2010-06-071-1/+1
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| | * | proper name for directoryMatt Ettus2010-06-071-1/+1
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| | * | name build directory with ISE version nameMatt Ettus2010-06-071-1/+1
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| | * | non-udp uses a different address for the tx dsp coreMatt Ettus2010-05-271-1/+1
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| | * | manual merge to use localparams from udp versionMatt Ettus2010-05-271-4/+23
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| | * | from UDP branch, changed names because I want these separate from the ↵Matt Ettus2010-05-273-0/+1321
| | | | | | | | | | | | | | | | non-udp versions
| | * | ignore output filesMatt Ettus2010-05-271-0/+2
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| | * | new files from udp branch added to main MakefileMatt Ettus2010-05-271-1/+19
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| | * | Merge branch 'udp' into master_merge_take2Matt Ettus2010-05-2730-67/+2257
| | |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * udp: (67 commits) better test program for just the tx side fix typo, no functionality difference ignores move dsp settings regs to reclocked setting bus. Works, gets us to within 18ps of passing timing reverting logic clean up which should have made timing better, but made it worse instead moved fifos around, now easier to see where they are and how big bigger fifo on UDP TX path, to possibly fix overruns on decim=4 Xilinx ISE is incorrectly parsing the verilog case statement, this is a workaround pps and vita time debug pins ignore emacs backup files more debug for fixing E's better debug pins for going after cascading E's copy in wrong place copied over from quad radio just debug pin changes typo caused the tx udp chain to be disconnected moved into subdir speed up timing by ignoring the too_early error. We'll need to FIXME this later Added set time and set time at next pps. Removed the old sync pps commands, they dont make sense to use anymore. moved around regs, added a bit to allow for alternate PPS source ...
| | | * | better test program for just the tx sideMatt Ettus2010-05-191-163/+63
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| | | * | fix typo, no functionality differenceMatt Ettus2010-05-191-1/+1
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| | | * | Merge branch 'master' into udpMatt Ettus2010-05-18224-329/+19
| | | |\ \ | | | |/ / | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | Remove CVS files, warning removal on setting reg width, aeMB synthesis pragmas Conflicts: usrp2/control_lib/setting_reg.v usrp2/top/u2_core/u2_core.v usrp2/top/u2_rev3/Makefile
| | * | | get rid of some warnings by declaring setting reg widthMatt Ettus2010-05-181-8/+8
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| | * | | added width parameter to avoid warnings (thanks IJB) and default value parameterMatt Ettus2010-05-181-3/+5
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| | * | | added pragmas suggested by Ian Buckley to help ISE12 synthesisMatt Ettus2010-05-181-3/+6
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| | * | | get rid of old CVS linkageMatt Ettus2010-05-18221-315/+0
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| | * | | settings bus to dsp_clk now uses clock crossing fifoMatt Ettus2010-05-162-8/+15
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| | | * | ignoresMatt Ettus2010-05-181-1/+1
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* | | | | Merge branch 'i2c_resize' into pre_mergeJosh Blum2010-06-185-11/+13
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| * | | | | usrp2 mb: replace hard coded constants with macros for rx offsetJosh Blum2010-06-181-2/+2
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| * | | | | usrp2: enlarged the i2c transaction size, rev-ed the firmware protocol ↵Josh Blum2010-06-174-9/+11
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* | | | | usrp2: code and comment tweak for aux dac callJosh Blum2010-06-171-4/+3
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* | | | | uhd: added enums for aux adc and dac, usrp2: implemented enums in db ifaceJosh Blum2010-06-175-22/+38
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* | | | | usrp2: implemented dboard clock divider control in usrp2 clock controlJosh Blum2010-06-171-8/+35
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* | | | | added set clock rate, and get clock rates to dboard iface, usrp2 needs clock ↵Josh Blum2010-06-174-3/+81
|/ / / / | | | | | | | | | | | | ctrl implementation...
* | | | uhd: check priority rangeJosh Blum2010-06-171-5/+4
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* | | | uhd: working windows implementation of thread priority setting, added called ↵Josh Blum2010-06-163-2/+14
| | | | | | | | | | | | | | | | to example apps
* | | | uhd: work on thread priority schedulingJosh Blum2010-06-169-65/+193
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* | | Merge branch 'sched'Josh Blum2010-06-155-1/+143
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| * | | uhd: added ability to boost rt priority, added general app notesJosh Blum2010-06-155-1/+143
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* | | | usrp2: added a type to the address args to filter based on type usrp2Josh Blum2010-06-151-1/+4
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* | | Merge branch 'work'Josh Blum2010-06-144-16/+73
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| * | | usrp2: improved print-out for socket buffer sizingJosh Blum2010-06-141-2/+5
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| * | | work on algorithms and documentationJosh Blum2010-06-143-14/+68
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* | | | Merge branch 'aux_dac'Josh Blum2010-06-146-21/+83
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| * | | usrp2: dboard iface: switched to nested dictionary for dac regsJosh Blum2010-06-141-8/+17
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| * | | Fixed USRP2 aux_dac numbering conventionJason Abele2010-06-114-16/+18
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| * | | created capability for meta-registersJosh Blum2010-06-092-2/+53
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* | | | Moved mux calculations into dsp type1 utils.Josh Blum2010-06-104-46/+59
| | | | | | | | | | | | | | | | Fixed error in db basic freq range switcheroo.
* | | | created uhd usrp probeJosh Blum2010-06-092-0/+170
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* | | fix for ad9862 regs mapJosh Blum2010-06-082-10/+11
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* | | fixed converter logic in convert typesJosh Blum2010-06-081-15/+16
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* | | extend byteswap routines for macosx, and added case for unknownJosh Blum2010-06-081-4/+32
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