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* X300: fix for incorrect PCIe buffer size valuesMatthew Crymble2020-08-043-5/+12
| | | | added extra args to get PCIe buffer sizes from factory method
* mpm: Reenable forward interfaces for remote hostsSteven Koo2020-08-041-2/+1
| | | | | The forward interfaces are able to forward CHDR packets with MPM iptables routing. This reenables forward interfaces as a CHDR option.
* x300: change default dboard clock rate from 50 to 100 MHzmattprost2020-08-045-42/+153
| | | | | | | | | | | | | | This sets the reference clock for X300 daughterboards (other than UBX) to 100 MHz by default to improve RF performance. Note: The UBX daughterboard requires a clock rate of no more than the max pfd frequency (50 or 25 MHz depending on the hardware rev) in order to maintain phase synchronization. If a UBX daughterboard is present on the X300, the clock rate for all daughterboards will be set to the pfd frequency by default. This is because of the limitation on X300 that requires the daughterboards to use the same clock rate. Signed-off-by: mattprost <matt.prost@ni.com>
* tests: Add graph disconnect/reconnect unit testmichael-west2020-08-041-0/+37
| | | | Signed-off-by: michael-west <michael.west@ettus.com>
* MPMD: Fix typomichael-west2020-08-041-1/+1
| | | | | | | Fix typo in warning message when DPDK is specified at run time but not enabled at compile time. Signed-off-by: michael-west <michael.west@ettus.com>
* RFNoC: Demote MTU message in radio controlmichael-west2020-08-041-1/+1
| | | | | | Change message from warning to debug when spp is greater than MTU. Signed-off-by: michael-west <michael.west@ettus.com>
* multi_usrp: Fix connect/disconnect of RFNoC chainsmichael-west2020-08-041-80/+202
| | | | | | | | | - Added helper methods to connect and disconnect TX and RX chains. - Directly create streamer objects and register local disconnect methods to make sure chains are disconnected and the streamer is removed from the graph when streamers are destroyed. Signed-off-by: michael-west <michael.west@ettus.com>
* RFNoC: Added support for destruction of streamersmichael-west2020-08-044-8/+52
| | | | | | | | | | | - Added rfnoc_graph method to disconnect a connection. - Added rfnoc_graph method to disconnect a streamer. - Added rfnoc_graph method to disconnect a port on a streamer. - Added disconnect callback to rfnoc_rx_streamer and rfnoc_tx_streamer. - Registered disconnect callback functions to streamers returned by get_rx_streamer and get_tx_streamer methods. Signed-off-by: michael-west <michael.west@ettus.com>
* RFNoC: Add disconnect methods to graphmichael-west2020-08-044-101/+364
| | | | | | | | | | - Added method to disconnect an edge - Added method to remove a node - Fixed algorithm to check edges during connect. Previous code was checking some edges twice and allowing duplicate edges to be created for existing edges. Signed-off-by: michael-west <michael.west@ettus.com>
* RFNoC: Add xport disconnect callbacksmichael-west2020-08-0410-43/+122
| | | | | | | | | | | | Transports were not disconnecting their links from the I/O service upon destruction, leaving behind inaccessible send and recv links used by nothing. This led to I/O errors after creating several transports. Added callbacks to transports to automatically disconnect their links from the I/O service when the transport is destroyed. Updated all callers to supply a disconnect callback. Signed-off-by: michael-west <michael.west@ettus.com>
* python: Add replay RFNoC block controller bindingsmattprost2020-08-043-0/+45
| | | | Signed-off-by: mattprost <matt.prost@ni.com>
* tests: Add Replay Block controller unit testmattprost2020-08-042-0/+764
| | | | Signed-off-by: mattprost <matt.prost@ni.com>
* rfnoc: Add RFNoC replay blockmattprost2020-08-045-202/+855
| | | | Signed-off-by: mattprost <matt.prost@ni.com>
* fpga: rfnoc: Add RFNoC Replay blockWade Fife2020-08-0412-875/+4164
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* fpga: rfnoc: Add 4 KiB boundary check to sim_axi_ramWade Fife2020-08-041-0/+12
| | | | | Adding a check for bursts that cross the 4 KiB boundary to the AXI4 memory model. Crossing a 4 KiB boundary is not allowed by AXI4.
* fpga: rfnoc: Add support for CHDR_W < ITEM_W*NIPCWade Fife2020-08-042-137/+195
| | | | | | | | | This change fixes the case where CHDR_W < ITEM_W*NIPC. It also adds a state machine to stall the input to the pyld_fifo to ensure that the pkt_info_fifo will not overflow. Previously in some cases it allowed the same word to be inserted into the pyld_fifo multiple times.
* fpga: lib: Fix comments and indentation in axi_fifo_short.vWade Fife2020-08-041-98/+87
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* python: Fix pyuhd to include subpackagesSamuel O'Brien2020-08-041-2/+6
| | | | | | | | | | | | | | | | | Originally, the setup.py file for pyuhd listed only one package packages=['uhd'] the setuptools docs: https://setuptools.readthedocs.io/en/latest/setuptools.html#using-find-packages specify that this should also include subpackages, i.e uhd.dsp, uhd.usrp, etc. Currently, when packaging libpyuhd, we are not including the subpackages, and then when you run `import uhd`, it fails because uhd.usrp and uhd.dsp don't exist. This commit alleviates this issue by using setuptools.find_packages like the docs recommend. Signed-off-by: Samuel O'Brien <sam.obrien@ni.com>
* cmake: don't try to determine runtime python version when cross compilingJoerg Hofrichter2020-08-041-9/+22
| | | | | | When cross compiling, the architecture of the runtime python interpreter does not match the host architecture. Therefore, don't try to detect it and set it to the min. supported python version instead.
* mpm: cmake: use UHDPython module to find PythonJoerg Hofrichter2020-08-041-10/+5
| | | | | Use UHDPython module (from UHD) to find Python interpreter, libraries and include directories.
* cmake: find python in sysroot path firstJoerg Hofrichter2020-08-041-0/+8
| | | | | | Set CMP0094 policy to NEW to make sure Python3 is first found in the SDK's sysroot if both the sysroot and the native paths are included in the PATH variable.
* cmake: tests: Support qemu also for python based testsJoerg Hofrichter2020-08-042-35/+71
| | | | This requires python3 to be installed in the target sysroot
* rfnoc: Fix compilation error when tracing enabledAaron Rossetto2020-07-311-2/+2
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* example: Check for failure in tx_samples_from_fileSamuel O'Brien2020-07-311-3/+9
| | | | | | | | | | | I was using this example for testing with the simulator. If there is a flow control failure, the original example would just silently finish, outputing the message "Done!" (Not even printing a timeout message). This commit asserts that the number of samples sent is equal to the number of samples provided. Signed-off-by: Samuel O'Brien <sam.obrien@ni.com>
* fpga: n320: Add BIST (AA) image filessteviez2020-07-315-0/+1148
| | | | | | | | | | This adds new image files which come with a DRAM FIFO. The addition of an N320 image with a DRAM FIFO allows DDR3 BIST to be run on an assembled (motherboard + daughterboard) N320. This image is intentionally very similar to the N300_AA and N310_AA targets which serve the same purpose of providing an image with a DRAM FIFO for their respective devices.
* utils: Use absolute paths in image builder build()steviez2020-07-311-2/+2
| | | | | | | A segment of the build() function updates the working directory. This change converts several paths to absolute paths to avoid having a relative path (such as one containing up-level references) deviate from its' intended meaning after the directory change.
* mpm: n3xx: bist: Read mboard and dboard eeprom to determine productSteve Czabaniuk2020-07-312-5/+14
| | | | | | | | The routine to identify products currently only reads the motherboard EEPROM. The N310 and N320/N321 use the same motherboard so these devices can't be distinguished using the motherboard EEPROM alone. This change makes get_product_id() read both the motherboard and daughterboard EEPROM in order to determine which N3xx it actually is.
* fpga: lib: Add xge features for new xport_svAndrew Moch2020-07-311-100/+191
| | | | | | | | | | - Made some things optional to reduce logic when used with the new xport_sv: (1) Clocking to sys_clk (2) Preamble insertion - New options to CUTTHROUGH faster on the TX path. The new xport_sv already has a gate to accumulate at its clock crossing.
* fpga: sim: Update PkgEthernetAndrew Moch2020-07-311-57/+91
| | | | | | Consolidated calcuation of last_tkeep and tkeep_last. Changed error checking to support unwrinkling tkeep/trailing changes in 100G etherent and support for testing packet dropping on backup.
* fpga: sim: Fix AxiLiteBfmAndrew Moch2020-07-311-3/+3
| | | | | AxiLiteBfm incorrectly included stb argument on rd() and printed actual response instead of expected in debug message.
* fpga: lib: Update AxiLiteIfAndrew Moch2020-07-311-1/+74
| | | | | This fixes a bug on wrstb in AxiLiteIf and adds a new AxiLiteIf_v that can be used to stitch onto Verilog port_maps.
* fpga: lib: Fix chdr_mgmt_pkt_handler when CHDR_W != 64Andrew Moch2020-07-301-1/+1
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* fpga: tools: RESOLVE_PATH checks for an empty pathAndrew Moch2020-07-301-4/+4
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* tests: Add unit test for siggen RFNoC block controllerAaron Rossetto2020-07-302-0/+352
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* python: Add siggen RFNoC block controller bindingsAaron Rossetto2020-07-303-0/+41
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* rfnoc: Add siggen RFNoC block controller supportAaron Rossetto2020-07-305-0/+553
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* fpga: rfnoc: Add Signal Generator RFNoC blockWade Fife2020-07-3013-18/+1980
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* fpga: lib: Add axis_packetize moduleWade Fife2020-07-302-0/+162
| | | | | | This module takes an AXI-Stream without TLAST and outputs the same AXI-Stream with TLAST based on the provided packet size input.
* python: Add Switchboard block python bindingsJesse Zhang2020-07-303-0/+24
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* rfnoc: Add Switchboard block unit testsJesse Zhang2020-07-302-0/+161
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* rfnoc: Add Switchboard block supportJesse Zhang2020-07-305-0/+181
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* fpga: Add Switchboard RFNoC blockJesse Zhang2020-07-308-0/+1162
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* mpm: Default virtual NIC CHDR IP selectionSteven Koo2020-07-306-16/+50
| | | | | This change adds detection for setting the correct internal fpga CHDR IP address when using embedded mode.
* images: Update manifestSteven Koo2020-07-291-10/+10
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* x300: Update maximum bitstream sizeWade Fife2020-07-281-1/+1
| | | | | | Add 2 bytes to account for Vivado update number, in addition to major, minor, and AR. For example the current Vivado version string might be 2019.1.1_AR73068 whereas the previous string was 2018.3_AR71898.
* mpm: Fix more gevent errors on SIGTERMSamuel O'Brien2020-07-281-6/+19
| | | | | | | | | | | | | Sometimes when running usrp_hwd.py in a terminal and then canceling it with Ctrl+C, it prints a really large stacktrace into the terminal resulting from an uncaught gevent BlockingSwitchOutError. This comes from trying to block on Process#join inside a gevent signal handler. This commit resolves this issue by simply triggering an event in the signal handler which prompts a different non-daemon thread to join the subprocesses and end the parent process. Signed-off-by: Samuel O'Brien <sam.obrien@ni.com>
* mpm: Fix documentation and minor issues in sys_utils.GPIOBankMartin Braun2020-07-281-6/+30
| | | | | | | | | | | - GPIOBank made the assumption that all bits used where contiguous. This amends the documentation to make that more clear, and adds an assert statement to check for that. - reset_all() would reset all pins, regardless of DDR value, rendering it useless for any GPIO bank that would want to have readable pins. Fixed that by checking DDR value before resetting. - Minor amendments to various docstrings; improve PyLint score by removing superfluous inheritance from object.
* docs: Fix daughterboard page formattingMartin Braun2020-07-241-3/+3
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* mpm: Fix gevent errors on SIGTERMSamuel O'Brien2020-07-242-5/+13
| | | | | | | | | | | | | | | | | | | | | | Sometimes when running usrp_hwd.py in a terminal and then canceling it with Ctrl+C, it prints a really large stacktrace into the terminal resulting from an uncaught gevent BlockingSwitchOutError. It seems like there was an attempt to catch this in usrp_hwd.py:kill_time(). This try-except was surrounding a call to Process.join() which, to the best of my knowledge, can't ever throw this exception. Based on my troubleshooting, this error comes from the SIGTERM signal handler of the RPC process. The handler (defined in rpc_server.py:_rpc_server_process), is just a direct call to RPCServer.stop(). When the server's backed is a thread pool, this call may block when joining the thread pool, causing gevent to complain about execution attempting to block in a signal handler. This commit resolves this issue by simply triggering an event in the signal handler which prompts a different thread to clean up the server and end the process. Signed-off-by: Samuel O'Brien <sam.obrien@ni.com>
* fpga, mpm: Bump FPGA compat numberRobertWalstab2020-07-246-6/+6
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