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| | | * | | | | | | | | | | Merge branch 'efifo_merge' of git@ettus.sourcerepo.com:ettus/fpgapriv into ↵Ian Buckley2010-09-015-47/+60
| | | |\ \ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | efifo_merge
| | | | * | | | | | | | | | | hangedddddddextrnal fifo size to use full NoBL SRAMianb2010-08-251-1/+1
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| | | | * | | | | | | | | | | Corrected extfifo code so that all registers that are on SRAM signals are ↵ianb2010-08-255-46/+59
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | packed into IOBs Explcit drives and skews added to GPIO pins Corrected minor error in FIFO logic that showed data avail internally incorrectly
| | | * | | | | | | | | | | | Enhanced test bench to be more like real world applicationIan Buckley2010-09-012-7/+14
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| | | * | | | | | | | | | | capacity logic fixMatt Ettus2010-08-191-1/+1
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| | | * | | | | | | | | | | Added capacity to the module pinoutIan Buckley2010-08-191-3/+4
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| | | * | | | | | | | | | | Added a bunch of debug signals.Ian Buckley2010-08-194-9/+19
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| | | * | | | | | | | | | | Merge branch 'ise12_efifo_work' into efifo_mergeMatt Ettus2010-08-198-236/+113
| | | |\ \ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * ise12_efifo_work: Regenerated FIFO with lower trigger level for almost full flag to reflect logic removed from nobl_fifo. Conflicts: usrp2/vrt/vita_tx_deframer.v
| | | | * | | | | | | | | | | Regenerated FIFO with lower trigger level for almost full flag to reflect ↵Ian Buckley2010-08-199-238/+115
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | logic removed from nobl_fifo. Improved ext_fifo_tb further, try to simulate more combinations of decomation rates and packet arrival patterns. Strip out the logic in nobl_fifo that made it look like a Xilinx fall-through FIFO...it is now very simple logic but a propriatory interface that exposes the high inetrnal latency of reads. Allow the USED size of the external FIFO to be parameterized from the core level. Currently set at only 256 Corrected a bug in vita_tx_deframer.v that can write to a FIFO when its full causing illegal state. Made further edits that are currently commented becuase simulation indicates they cause problems, however suspect a further bug is in this code.
| | | * | | | | | | | | | | | Merge branch 'features' into ise12_efifo_mergeMatt Ettus2010-08-162-3/+6
| | | |\ \ \ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * features: added compat number to usrp2 readback mux makefile dependency fix for second expansion
| | | * \ \ \ \ \ \ \ \ \ \ \ \ Matt's attempt at mergingMatt Ettus2010-08-1610-5569/+306
| | | |\ \ \ \ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Merge branch 'tx_policy' into ise12_efifo_work * tx_policy: rx error context packets should not be marked as errors in the fifo provide a way to get out of the error state without processor intervention sequence number reset upon programming streamid attempt at avoiding infinite error messages implemented "next packet" and "next burst" policies sequence errors can happen on start of burst as well. more informative error codes cleaner error handling introduce new error types test mux and gen_context_pkt this is an output file, it shouldn't be checked in insert protocol engine flags when requested move the streamid so it isn't at the same address as clear_state connect the demux fix a typo tx error packets now muxed into the ethernet stream back to the host checkpoint. New context packet generator to report underruns and other errors Conflicts: usrp2/top/u2_rev3/u2_core_udp.v
| | | * \ \ \ \ \ \ \ \ \ \ \ \ \ Merge branch 'ise12' into ise12_efifo_workMatt Ettus2010-08-1610-33/+180
| | | |\ \ \ \ \ \ \ \ \ \ \ \ \ \ | | | | |_|_|/ / / / / / / / / / / | | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * ise12: move declaration ahead of use put run_tx and run_rx on the displayed LEDs remove warnings add mux and demux to build mux multiple fifo streams into one. Allows priority or round robin split fifo into 2 streams based on first line in each packet fix to stop endless error packets updated tests to match new features error packets are now valid Extension Context packets error packets don't have a trailer any more streamid is now optional on data packets, set by header register trailer now has a bit to indicate successful End-of-burst hard-coded some header bits to correct values to ensure valid packets reload bit for vita rx ctrl
| | | * | | | | | | | | | | | | | Regenerated FIFO's for extfifo.Ian Buckley2010-08-1212-728/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are problems with certain configurations it seems. It is important that the fifo_xlnx_512x36_2clk_18to36 is generated with the "almost_full" pin even though it is not used in the application. if this pin is omitted the FPGA image doesn't work correctly
| | | * | | | | | | | | | | | | | Edited FIFO instance to delete port that was not regenerated after ↵Ian Buckley2010-08-121-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | reconfiguration
| | | * | | | | | | | | | | | | | Adding in files that probably didn;t exist in the ISE10.1 version of coregenIan Buckley2010-08-125-0/+808
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| | | * | | | | | | | | | | | | | Bringing all coregen files checked in into syncIan Buckley2010-08-1210-137/+60
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| | | * | | | | | | | | | | | | | Merge branch 'ise12_efifo_work' of git@ettus.sourcerepo.com:ettus/fpgapriv ↵Ian Buckley2010-08-1218-41/+587
| | | |\ \ \ \ \ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into ise12_efifo_work Conflicts: usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.ngc usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.v usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.xco usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.ngc Resolving conflicts by regenerating files clenly in ISE12.1 coregen
| | | | * | | | | | | | | | | | | | checkin of generated coregen filesMatt Ettus2010-08-1118-8/+556
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| | | * | | | | | | | | | | | | | | Found bug due to not accounting for the correct number of possible in flight ↵Ian Buckley2010-08-127-49/+113
| | | |/ / / / / / / / / / / / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | READ operations that can be in the extfifo pipeline. Regenerated fifo_xlnx_512x36_2clk_18to36 to include prog_full output triggered at 1017 so that there are 6 empty spaces to accept in flight read data upon completion. Had to generate the FIFO using Coregen from ISE12.1 due to 10.1 verion not working correctly in FPGA Still have to tackle making this simulate in Icarus
| | | * | | | | | | | | | | | | | External FIFO tested in simulation and on USRP2 from decimation 64->8 with ↵Ian Buckley2010-07-3119-238/+7327
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | current head UHD code. Apparently operation is "flawless" but more regression and corner case regression could and should be done. Tristate drivers have been added at the top level of the hierarchy for the SRAM databus as is considered good practice for both Xilinx and ASIC design flows and so both top level and core fils have been touched.
| | | * | | | | | | | | | | | | | Checkpoint checkin.Ian Buckley2010-07-2913-0/+1507
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Loopback is running via the external ZBT SRAM...HOWEVER, its not running well, its stable but the data is corrupted sometimes. Not clear if its a logic or AC timing/SI issue yet.
| | | * | | | | | | | | | | | | | get it to buildMatt Ettus2010-07-145-5/+309
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| | | * | | | | | | | | | | | | | moved forward from the old branchMatt Ettus2010-07-148-4/+876
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| | * | | | | | | | | | | | | | | uhd: removed 1 sample buffers in test async messagesJosh Blum2010-10-142-8/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | made a hack in the vrt handler to bump 0 sample requests up to 1 sample (until the hardware supports it)
| | * | | | | | | | | | | | | | | usrp2: move udp port initialization into mboard impl so its done before ↵Josh Blum2010-10-144-15/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | async registers are setup
| | * | | | | | | | | | | | | | | usrp2: handle destination port unreachable icmp in fw (kills streaming and ↵Josh Blum2010-10-132-1/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | update packets)
| | * | | | | | | | | | | | | | | udp: fix to use concurrency hint, default hint is zero when no async enabledJosh Blum2010-10-132-11/+21
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| | * | | | | | | | | | | | | | | usrp2: added docs on flow control ricer args and using usrp2 with a switchJosh Blum2010-10-136-25/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | implemented flow control param hints in the mboard impl
| | * | | | | | | | | | | | | | | usrp: test async messages app randomly runs testsJosh Blum2010-10-131-17/+67
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| | * | | | | | | | | | | | | | | usrp2: increment tx sequence after commitJosh Blum2010-10-132-1/+3
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| | * | | | | | | | | | | | | | | usrp2: register overflow, underflow, and pps level for picJosh Blum2010-10-122-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | also fix minor build issue w/ LDADD
| | * | | | | | | | | | | | | | | uhd: test eob ack message, usrp2: remove rx drain on init with the promise ↵Josh Blum2010-10-123-19/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | of a reset register
| | * | | | | | | | | | | | | | | usrp2: enable the cycles per ack, and drain recv without the timeout (fixes ↵Josh Blum2010-10-112-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | previous conflict)
| | * | | | | | | | | | | | | | | usrp2: use select rather than manually polling the simple udp socketJosh Blum2010-10-114-31/+26
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| | * | | | | | | | | | | | | | | usrp2: use 32-bit flow control sequence numbersJosh Blum2010-10-113-20/+15
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| | * | | | | | | | | | | | | | | usrp2: implemented flow control monitorJosh Blum2010-10-116-22/+110
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | set registers in mboard impl to enable asyn fc packets modified microblaze code to handle dummy data packet offset
| | * | | | | | | | | | | | | | | usrp2: add fc control registers, use small timeout for control packets againJosh Blum2010-10-112-11/+6
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| | * | | | | | | | | | | | | | | usrp2: implement fc seq number on tx header packingJosh Blum2010-10-113-25/+41
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* | | | | | | | | | | | | | | | | usrp: removed deprecated interfaces simple and mimoJosh Blum2010-11-233-915/+0
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* | | | | | | | | | | | | | | | | uhd: new versioning scheme with API compat numberJosh Blum2010-11-231-13/+6
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* | | | | | | | | | | | | | | | | uhd: added printable to string methods to rangesJosh Blum2010-11-231-0/+1
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* | | | | | | | | | | | | | | | | N200 comes up with default IP and MAC when booted in safe mode (button pushed).Nick Foster2010-11-227-21/+59
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* | | | | | | | | | | | | | | | | usrp2: ms didnt seem to like unlocking an unlocked mutexJosh Blum2010-11-221-3/+4
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* | | | | | | | | | | | | | | | Merge branch 'mac_fixes' into ranges_fixJosh Blum2010-11-172-6/+22
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| * | | | | | | | | | | | | | | | uhd: git diffJosh Blum2010-11-171-6/+9
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| * | | | | | | | | | | | | | | | udp: added polling alternative to select for macJosh Blum2010-11-171-0/+13
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* | | | | | | | | | | | | | | | | uhd: tweaking the export template instance macroJosh Blum2010-11-172-5/+8
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* | | | | | | | | | | | | | | | | uhd: added to printable string methods for rangesJosh Blum2010-11-172-2/+26
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* | | | | | | | | | | | | | | | uhd: ranges symbol fix, try extern macroJosh Blum2010-11-173-2/+12
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* | | | | | | | | | | | | | | | usrp: use a spawn thread to ensure that a pirate is spawned before ↵Josh Blum2010-11-161-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | continuing (fixes lockup issue)