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* fpga: tools: Put SIM_SRCS at end of compile orderWade Fife2021-06-171-1/+1
| | | | | | VHDL depends on the compile order. This commit changes the order so that SIM_SRCS are compiled last with ModelSim to avoid issues with dependencies.
* fpga: tools: Support new FPGA types in viv_simulator.makWade Fife2021-06-171-2/+2
| | | | | | This updates the existing PART_NAME generation used in simulation makefiles to work with newer part families by calling viv_gen_part_id.py to generate the part name needed by Vivado.
* fpga: tools: Fix python2 reference in viv_ip_builder.makWade Fife2021-06-171-1/+1
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* fpga: tools: Add modelsim.excludesWade Fife2021-06-171-0/+18
| | | | | This is a list of testbenches that don't work with ModelSim and should be excluded when running run_testbenches.py.
* fpga: tools: Add modelsim.ini to ModelSim callsWade Fife2021-06-174-7/+38
| | | | | | | | | | | This adds the MSIM_VIV_COMPLIBDIR environment variable to specify a non-default location for the compilation libraries. This also allows a modelsim.ini other than the one in the ModelSim installation folder to be used. By default, the one in the simulation libraries compilation directory will be used. This can be changed by setting MSIM_MODELSIM_INI to the one you want to use, or set it to an empty string to use the one in the ModelSim installation folder.
* fpga: tools: Add features to run_testbenches.pyWade Fife2021-06-171-6/+19
| | | | | | | | | | | | | | | | Run "make ip" in a separate step for each testbench. This allows some testbenches to work better with ModelSim because it needs IP files that aren't known until after the IP is generated. Make run_testbenches.py more log friendly. Add a -l/--logged option for when the output is being logged. In this case, we don't want to display elapsed time every second. Add "Begin TB Log:" and "End TB Log:" to the output to more easily tell where the output from one testbench ends and another begins. Use the basedir argument as the base directory in which to search for testbenches so that a subset of the repo can be easily specified.
* fpga: tools: Add ip target to simulation makefilesWade Fife2021-06-172-2/+6
| | | | | Allow building of just the IP by running "make ip" in simulation directories.
* uhd: Update versionAaron Rossetto2021-06-161-1/+1
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* docs: zbx: improve cpld update docsMichael Auchter2021-06-161-7/+5
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* docs: usrp_x4xx: improve mb cpld update docsMichael Auchter2021-06-161-3/+2
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* mpm: install cpld update scripts in runtime dirMichael Auchter2021-06-161-0/+10
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* mpm: x4xx_bist: run spi_flash tests on both DBsMichael Auchter2021-06-151-9/+29
| | | | | By default, run the spi_flash tests on both daughterboards instead of only the first one.
* uhd: x400: Honor ENABLE_X400 component flagAaron Rossetto2021-06-151-9/+14
| | | | Don't add X400-related sources to libuhd if they are not requested.
* images: Update manifestAaron Rossetto2021-06-111-12/+12
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* mpm: max10_cpld_flash_ctrl: only reprogram cpld if necessaryMichael Auchter2021-06-101-0/+8
| | | | | | | When updating the CPLD via the flash method, first read back the CPLD image from flash and compare it with the image to be programmed. If they match, the CPLD is already running the correct image and reprogramming it is not necessary.
* uhd: ci: Add test definition for UHD CIJoerg Hofrichter2021-06-105-2/+449
| | | | | Co-authored-by: Joerg Hofrichter <joerg.hofrichter@ni.com> Co-authored-by: Cristina Fuentes <cristina.fuentes@ni.com>
* uhd: Add support for the USRP X410Lars Amsel2021-06-10185-160/+61559
| | | | | | | | | | | | | | | | Co-authored-by: Lars Amsel <lars.amsel@ni.com> Co-authored-by: Michael Auchter <michael.auchter@ni.com> Co-authored-by: Martin Braun <martin.braun@ettus.com> Co-authored-by: Paul Butler <paul.butler@ni.com> Co-authored-by: Cristina Fuentes <cristina.fuentes-curiel@ni.com> Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com> Co-authored-by: Virendra Kakade <virendra.kakade@ni.com> Co-authored-by: Lane Kolbly <lane.kolbly@ni.com> Co-authored-by: Max Köhler <max.koehler@ni.com> Co-authored-by: Andrew Lynch <andrew.lynch@ni.com> Co-authored-by: Grant Meyerhoff <grant.meyerhoff@ni.com> Co-authored-by: Ciro Nishiguchi <ciro.nishiguchi@ni.com> Co-authored-by: Thomas Vogel <thomas.vogel@ni.com>
* images: add X410 series FPGA imagesJoerg Hofrichter2021-06-101-0/+6
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* fpga: tools: Add X410 support for image packagingHumberto Jimenez2021-06-101-0/+24
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* fpga: ci: Add build definitions for FPGA CIWade Fife2021-06-107-0/+483
| | | | | | | Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com> Co-authored-by: Javier Valenzuela <javier.valenzuela@ni.com> Co-authored-by: Max Köhler <max.koehler@ni.com> Co-authored-by: Paul Butler <paul.butler@ni.com>
* fpga: x400: zbx: Add support for ZBX CPLDJavier Valenzuela2021-06-1037-0/+17727
| | | | | | | Co-authored-by: Cherwa Vang <cherwa.vang@ni.com> Co-authored-by: Martin Braun <martin.braun@ettus.com> Co-authored-by: Max Köhler <max.koehler@ni.com> Co-authored-by: Paul Butler <paul.butler@ni.com>
* fpga: x400: cpld: Add support for X410 motherboard CPLDMax Köhler2021-06-1042-0/+8377
| | | | | Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com> Co-authored-by: Javier Valenzuela <javier.valenzuela@ni.com>
* fpga: x400: Add support for X410 motherboard FPGAWade Fife2021-06-10207-1/+299667
| | | | | | | | | | | | | Co-authored-by: Andrew Moch <Andrew.Moch@ni.com> Co-authored-by: Daniel Jepson <daniel.jepson@ni.com> Co-authored-by: Javier Valenzuela <javier.valenzuela@ni.com> Co-authored-by: Joerg Hofrichter <joerg.hofrichter@ni.com> Co-authored-by: Kumaran Subramoniam <kumaran.subramoniam@ni.com> Co-authored-by: Max Köhler <max.koehler@ni.com> Co-authored-by: Michael Auchter <michael.auchter@ni.com> Co-authored-by: Paul Butler <paul.butler@ni.com> Co-authored-by: Wade Fife <wade.fife@ettus.com> Co-authored-by: Hector Rubio <hrubio@ni.com>
* fpga: sim: Add slave_idle() to PkgAxiStreamBfm.svWade Fife2021-06-101-0/+4
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* fpga: lib: Update register comments in eth_regs.vhWade Fife2021-06-101-1/+5
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* fpga: Update rfnoc_image_core for all targetsWade Fife2021-06-1018-5780/+6492
| | | | | | Update rfnoc_image_core.v to take into account the new image_core_name fields and version strings. Add new rfnoc_image_core.vh. Update YAML where needed.
* fpga: Update recommended HDL header guidelineWade Fife2021-06-101-0/+3
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* transport: Set mtu to 9000 for all 10GbE use casesmattprost2021-06-103-8/+8
| | | | | | | | An default MTU value of 9000 gives the devices the most flexibility using 10GbE. Many interfaces and docs have already been updated. This is bringing all devices into alignment with this paradigm. Signed-off-by: mattprost <matt.prost@ni.com>
* fpga: tools: Fix part selection in setupenvSam O'Brien2021-06-101-4/+12
| | | | | | | | | | | | | | The script setupenv_base.sh, which is used to setup the development environmnet in the open source toolchain, adds some functions to the shell that are used to interact with vivado. Some of the functions were looking in the wrong argument for the product name. This commit fixes the bug. In addition, supplying an incorrect part name returned a rather opaque error message. This commit also fixes the error handling so that the intended error message is displayed. Signed-off-by: Sam O'Brien <sam.obrien@ni.com>
* cal: Add min_freq and max_freq attributes to USRPCalibratorBaseMartin Braun2021-06-101-2/+4
| | | | | | | These allow specifying a min/max frequency on a device basis, instead of querying those from get_?x_freq_range(). The trouble with those methods is, they include the tune range provided by DSP tuning, which is not what we want for this calibration.
* cal: Fix minor issues in the calibration utilitiesMartin Braun2021-06-104-14/+15
| | | | | | - Whitespace issues - Unclear help messages - Unnecessary derive-from-object
* devtest: benchmark_rate: Add support for rx and tx only testsmattprost2021-06-101-19/+27
| | | | | | | Fixes some minor reporting issues that occurred in devtest streaming tests with only rx or only tx. Signed-off-by: mattprost <matt.prost@ni.com>
* multi_usrp: Factor out make_overall_tune_range() and fix limitsMartin Braun2021-06-093-42/+39
| | | | | | | | | This function had an issue where it might return negative frequency values. A quick fix was to limit it to positive frequencies. Since this function was duplicated between multi_usrp and multi_usrp_rfnoc, this patch also moves it to a common location to not have to fix it twice.
* mpmd: support four linksAndrew Lynch2021-06-082-0/+10
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* fpga: Change RFNoC YAML version numbers to stringsWade Fife2021-06-0834-68/+68
| | | | | Change version from a numeric to a string, in order to differentiate between versions like "1.1" and "1.10".
* images: Update manifestAaron Rossetto2021-06-081-8/+8
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* dboard_iface: Fix sleep()michael-west2021-06-031-1/+1
| | | | | | Sleep was incorrectly in nanosecond counts instead of microsecond counts. Signed-off-by: michael-west <michael.west@ettus.com>
* rfnoc: Fix post action behavior of nodesLars Amsel2021-06-031-0/+4
| | | | | | | | | | | When a node has an action callback assigned this must be cleared along with the block removal. Otherwise a post action callback might try to modify node that are already removed which results in an undefined behavior. In particular this one fixes the Unexpected error [ERROR] [CTRLEP] Caught exception during async message handling: map::at when running the multi_usrp_test.py
* fpga: lib: Add modports to SV AXI-Stream blocksWade Fife2021-06-034-8/+8
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* fpga: lib: Add time_increment port to timekeeperWade Fife2021-06-031-17/+43
| | | | | Adds a time_increment port for situations in which the parameter TIME_INCREMENT can't be used. They offer the same behavior.
* fpga: lib: Pipeline ctrlport_timerWade Fife2021-06-031-24/+81
| | | | | | | This pipelines ctrlport_timer to eliminate the long combinational path caused by the time comparisons. This change also removes the PRECISION_BITS parameter and converts it to a signal named time_ignore_bits.
* fpga: lib: Add clock domain comments to interfacesWade Fife2021-06-037-13/+28
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* fpga: lib: Add 2 to 1 gearbox moduleWade Fife2021-06-035-0/+517
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* fpga: lib: Add PHASE parameter to sim_clk_genWade Fife2021-06-031-1/+3
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* fpga: lib: Add AXI4 (full) interfaceAndrew Moch2021-06-034-0/+619
| | | | | Add a SystemVerilog interface for connecting AXI4 ports, and an associated header file with helper macros.
* fpga: lib: add pause support to ethernet xportAndrew Moch2021-06-036-7/+112
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* fpga: lib: Add eth_ipv4_internalWade Fife2021-06-032-0/+442
| | | | | This adds a generic version of eth_internal that allows you to specify the CHDR width.
* fpga: lib: Add zynquplus family to axi_bitqHumberto Jimenez2021-06-031-12/+13
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* fpga: tools: Add ability to run commands before routeWade Fife2021-06-031-5/+11
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* fpga: tools: Add ability to patch IP during generationWade Fife2021-06-032-0/+87
| | | | | | This adds the ability to call BUILD_VIVADO_IP, as before, followed by REBUILD_VIVADO_IP_WITH_PATCH to patch a file generated by the IP and then rebuild the IP with the patched file.
generated by cgit v1.2.3 (git 2.39.1) at 2025-01-02 17:24:13 +0000