| Commit message (Collapse) | Author | Age | Files | Lines |
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Normally high, goes low when pushed
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* ise12:
move declaration ahead of use
put run_tx and run_rx on the displayed LEDs
remove warnings
add mux and demux to build
mux multiple fifo streams into one. Allows priority or round robin
split fifo into 2 streams based on first line in each packet
fix to stop endless error packets
updated tests to match new features
error packets are now valid Extension Context packets error packets don't have a trailer any more streamid is now optional on data packets, set by header register trailer now has a bit to indicate successful End-of-burst hard-coded some header bits to correct values to ensure valid packets
reload bit for vita rx ctrl
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has already incremented by the time the data is returned
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unused write port on a ram
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* ise12:
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* ise12:
precompute udp checksums
barely fails timing on gigE/10 and gigE/12, larger fail on udp/10, but all seem to work ok
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* master:
fix bug which caused serdes fifo to disappear
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* master:
proper dependency tracking for the makefile
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* master:
new make works on ise12
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* master:
produces good bin files
first attempt at cleaning up the build system
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* master:
get rid of debug stuff to help timing
move u2_core into u2_rev3 directory to simplify directory structure and save headaches
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* master:
allow other clock rates in vita time
report ise version in build
proper name for directory
name build directory with ISE version name
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Conflicts:
images/Makefile
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After loading the module, we need to wait until /dev/usrp_e0 is available
before proceeding.
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usrp_e100_i2c
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fixed char cast (to treat like integer)
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e100 eeprom map
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Conflicts:
host/utils/CMakeLists.txt
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