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* e100: tighten timing - less routing on EM_AJosh Blum2012-07-194-4/+4
| | | | | There were a few places it was ok to use addr over EM_A. This makes routing sligtly easier for GPMC signals.
* u1plus: added sr misc hook for clock syncJosh Blum2012-07-181-1/+8
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* e100: renamed top level for E100/E110 to E1x0Josh Blum2012-07-176-16/+16
| | | | Some minor tweaks to gpmc_to_fifo + timing
* E100: squash E100/E110 top level workJosh Blum2012-07-166-531/+84
| | | | | | Implements timed commands and FIFO control. Uses control and data FIFOs for GPMC. Uses the common core for E100/B100.
* gpmc: squashed GPMC FIFO work for E100Josh Blum2012-07-165-162/+93
| | | | | The control and data slaves are now both implemented as FIFOs. Requires another squash of E100 top level to use.
* gpmc: tighter timing constraints and easier to route gpmc to fifoJosh Blum2012-07-162-26/+37
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* Merge branch 'master' into nextJosh Blum2012-07-163-43/+6
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| * Merge branch 'maint'Josh Blum2012-07-163-43/+6
| |\ | | | | | | | | | | | | Conflicts: usrp2/top/E1x0/u1e_core.v
| | * e100: offset gpmc to fifo writes by 2 transfersJosh Blum2012-07-152-5/+5
| | | | | | | | | | | | This effectivly works around bus initial transaction issues.
| | * e100: reverted commit registering in gpmcJosh Blum2012-07-151-38/+1
| | | | | | | | | | | | There is a subtle bus issue that the last changset did not address.
* | | B100: squash B100 top level workJosh Blum2012-07-024-406/+348
| | | | | | | | | | | | | | | | | | Implements timed commands and FIFO control. Uses control and data FIFOs for GPIF. Implements a common core for E100/B100.
* | | gpif: squashed GPIF slave fifo work for B100Josh Blum2012-07-024-414/+319
| | | | | | | | | | | | | | | The control and data enpoints are now both implemented as FIFOs. Requires another squash of B100 top level to use.
* | | fifo: added module packet_padder36 to fifo/Josh Blum2012-07-022-1/+157
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* | b100: removed unused proto filesJosh Blum2012-06-133-390/+0
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* | fpga: added setting regs based simple_i2c_coreJosh Blum2012-05-302-0/+117
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* | fpga: added some parameterization to settings_fifo_ctrlJosh Blum2012-05-301-3/+6
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* | fpga: added various models from ISEJosh Blum2012-05-307-0/+4011
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* | Merge branch 'maint'Josh Blum2012-05-221-1/+38
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| * Added registers for gpmc-to-fifo interface to address sequence errors for ↵Al Fayez2012-05-221-1/+38
| | | | | | | | E100/E110
* | Merge branch 'maint'Josh Blum2012-05-102-7/+9
|\| | | | | | | | | Conflicts: usrp2/top/E1x0/u1e_core.v
| * e100: bump compat minor for xclock reader fixJosh Blum2012-05-101-1/+1
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| * fpga: xclock fix for edge case conditionJosh Blum2012-05-081-6/+8
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* | e100/b100: bumped compat number for timed commands mergeJosh Blum2012-04-252-2/+2
| | | | | | | | | | There were common FPGA changes and an incompatibility. This should have been done before the merge anyhow.
* | slave_fifo: use 2KB FIFO size instead of 1KBNick Foster2012-04-241-1/+1
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* | b100: implement packet-end/flush cycle timeoutJosh Blum2012-04-243-12/+26
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* | gpif: removed unused gpif related filesJosh Blum2012-04-248-908/+1
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* | N2x0: updated the bootloader w/ latest from fwJosh Blum2012-04-201-390/+390
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* | usrp2: remove settings_fifo_ctrl, meets timingJosh Blum2012-04-201-2/+11
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* | fifo ctrl: Nseries timing meets with a single shortfifoJosh Blum2012-04-171-3/+2
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* | usrp: work on meeting timing constraintsJosh Blum2012-04-105-25/+30
| | | | | | | | | | | | * fifo ctrl register the vita ticks and use late * vita de/framer make nchans const since we dont change it * simplify readback muxes to minimal usage
* | Merge branch 'master' into nextJosh Blum2012-04-095-7/+67
|\ \ | | | | | | | | | | | | | | | Conflicts: usrp2/top/N2x0/u2plus_core.v usrp2/top/USRP2/u2_core.v
| * | Merge branch 'maint'Josh Blum2012-04-095-6/+6
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| | * vita: moved clear register to overlap with nchan registerJosh Blum2012-04-095-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This fixes the bug where setting the format clears the vita RX. This is only an issue when the noclear option is set by UHD, because the format register is always so, so it always clears. Note: noclear is there to support the backwards compat API (pre streamer). Now, numchans and clear overlap. This is ok because in the host code, clear and numchans are always used together. All timing meets on N2xx and USRP2.
| * | Merge branch 'maint'Josh Blum2012-04-022-5/+5
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| | * b100: fix slave fifo data xfer exit conditionJosh Blum2012-04-012-5/+5
| | | | | | | | | | | | | | | | | | | | | When exiting the read/write data state, when the transfer count maxes out/peaks, the fifo read/write signals were getting this condition the cycle after with the state change.
| * | fpga: extract usage summary from map fileJosh Blum2012-03-271-0/+60
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* | Merge branch 'master' into nextJosh Blum2012-03-264-85/+92
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| * B100: port cleanups from b100-txbug to this branchNick Foster2012-03-262-28/+21
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| * fpga: fifo_2clock handles widths and sizes in-between corgensJosh Blum2012-03-251-21/+23
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| * b100: cleanup redundant logic for slwr and slrdJosh Blum2012-03-251-2/+2
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| * b100: extra data pktend cycle for fifo addrJosh Blum2012-03-251-2/+8
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| * b100: slave fifo fix for dst/src ready signalsJosh Blum2012-03-242-35/+41
| | | | | | | | | | | | | | | | Some of the changes my be overkill, but the idea is to be more careful about allowing FIFO IO to occur on transitions. The cal app was able to complete successfully.
* | spi core: ready logic low one cycle earlierJosh Blum2012-03-161-1/+1
| | | | | | | | | | | | | | FIFO ctrl can poke registers every other cycle, the extra time to register not ready for spi core was too long. And it with ~trigger to get the not-ready one cycle earlier, so FIFO ctrl can block on the 2nd potential spi transaction.
* | fifo ctrl: parameterize having a proto headerJosh Blum2012-03-164-10/+12
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* | fifo ctrl: rename fifo ctrl module and add sid ack paramJosh Blum2012-03-164-37/+40
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* | fifo ctrl: minor fixes for spi core, swap time defineJosh Blum2012-03-165-10/+10
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* | fifo ctrl: simplified perfs, added spi clock idle phaseJosh Blum2012-03-165-333/+341
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* | fifo ctrl: minor fixes from last commitJosh Blum2012-03-163-366/+366
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* | fifo ctrl: spi core work, fifo ctrl perifs, usrp2 supportJosh Blum2012-03-165-370/+429
| | | | | | | | | | | | | | | | Continued work on simple spi core. Added peripherals input to fifo ctrl so perifs can backpressure fifo ctrl. Copied the implementation into usrp2 core.
* | spi: created simple spi core (sr based)Josh Blum2012-03-164-383/+593
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