Commit message (Collapse) | Author | Age | Files | Lines | ||
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| | * | | | | | Bringing all coregen files checked in into sync | Ian Buckley | 2010-08-12 | 10 | -137/+60 | |
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| | * | | | | | Merge branch 'ise12_efifo_work' of git@ettus.sourcerepo.com:ettus/fpgapriv ↵ | Ian Buckley | 2010-08-12 | 18 | -41/+587 | |
| | |\ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into ise12_efifo_work Conflicts: usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.ngc usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.v usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.xco usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.ngc Resolving conflicts by regenerating files clenly in ISE12.1 coregen | |||||
| | | * | | | | | checkin of generated coregen files | Matt Ettus | 2010-08-11 | 18 | -8/+556 | |
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| | * | | | | | | Found bug due to not accounting for the correct number of possible in flight ↵ | Ian Buckley | 2010-08-12 | 7 | -49/+113 | |
| | |/ / / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | READ operations that can be in the extfifo pipeline. Regenerated fifo_xlnx_512x36_2clk_18to36 to include prog_full output triggered at 1017 so that there are 6 empty spaces to accept in flight read data upon completion. Had to generate the FIFO using Coregen from ISE12.1 due to 10.1 verion not working correctly in FPGA Still have to tackle making this simulate in Icarus | |||||
| | * | | | | | External FIFO tested in simulation and on USRP2 from decimation 64->8 with ↵ | Ian Buckley | 2010-07-31 | 19 | -238/+7327 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | current head UHD code. Apparently operation is "flawless" but more regression and corner case regression could and should be done. Tristate drivers have been added at the top level of the hierarchy for the SRAM databus as is considered good practice for both Xilinx and ASIC design flows and so both top level and core fils have been touched. | |||||
| | * | | | | | Checkpoint checkin. | Ian Buckley | 2010-07-29 | 13 | -0/+1507 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Loopback is running via the external ZBT SRAM...HOWEVER, its not running well, its stable but the data is corrupted sometimes. Not clear if its a logic or AC timing/SI issue yet. | |||||
| | * | | | | | get it to build | Matt Ettus | 2010-07-14 | 5 | -5/+309 | |
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| | * | | | | | moved forward from the old branch | Matt Ettus | 2010-07-14 | 8 | -4/+876 | |
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| * | | | | | | uhd: removed 1 sample buffers in test async messages | Josh Blum | 2010-10-14 | 2 | -8/+13 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | made a hack in the vrt handler to bump 0 sample requests up to 1 sample (until the hardware supports it) | |||||
| * | | | | | | usrp2: move udp port initialization into mboard impl so its done before ↵ | Josh Blum | 2010-10-14 | 4 | -15/+16 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | async registers are setup | |||||
| * | | | | | | usrp2: handle destination port unreachable icmp in fw (kills streaming and ↵ | Josh Blum | 2010-10-13 | 2 | -1/+13 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | update packets) | |||||
| * | | | | | | udp: fix to use concurrency hint, default hint is zero when no async enabled | Josh Blum | 2010-10-13 | 2 | -11/+21 | |
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| * | | | | | | usrp2: added docs on flow control ricer args and using usrp2 with a switch | Josh Blum | 2010-10-13 | 6 | -25/+46 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | implemented flow control param hints in the mboard impl | |||||
| * | | | | | | usrp: test async messages app randomly runs tests | Josh Blum | 2010-10-13 | 1 | -17/+67 | |
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| * | | | | | | usrp2: increment tx sequence after commit | Josh Blum | 2010-10-13 | 2 | -1/+3 | |
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| * | | | | | | usrp2: register overflow, underflow, and pps level for pic | Josh Blum | 2010-10-12 | 2 | -2/+3 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | also fix minor build issue w/ LDADD | |||||
| * | | | | | | uhd: test eob ack message, usrp2: remove rx drain on init with the promise ↵ | Josh Blum | 2010-10-12 | 3 | -19/+20 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | of a reset register | |||||
| * | | | | | | usrp2: enable the cycles per ack, and drain recv without the timeout (fixes ↵ | Josh Blum | 2010-10-11 | 2 | -3/+4 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | previous conflict) | |||||
| * | | | | | | usrp2: use select rather than manually polling the simple udp socket | Josh Blum | 2010-10-11 | 4 | -31/+26 | |
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| * | | | | | | usrp2: use 32-bit flow control sequence numbers | Josh Blum | 2010-10-11 | 3 | -20/+15 | |
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| * | | | | | | usrp2: implemented flow control monitor | Josh Blum | 2010-10-11 | 6 | -22/+110 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | set registers in mboard impl to enable asyn fc packets modified microblaze code to handle dummy data packet offset | |||||
| * | | | | | | usrp2: add fc control registers, use small timeout for control packets again | Josh Blum | 2010-10-11 | 2 | -11/+6 | |
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| * | | | | | | usrp2: implement fc seq number on tx header packing | Josh Blum | 2010-10-11 | 3 | -25/+41 | |
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* | | | | | | | uhd: fix docs on boost version, also add additional version string for 1.44 | Josh Blum | 2010-10-14 | 2 | -2/+2 | |
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* | | | | | | | Added documentation of daughterboard filter bandwidths | Jason Abele | 2010-10-12 | 1 | -3/+15 | |
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* | | | | | | | Enhance XCVR2450 to clip for high/low band tuning and add bandwidth property | Jason Abele | 2010-10-12 | 2 | -9/+149 | |
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* | | | | | | | Merge branch 'set_bandwidth' | Josh Blum | 2010-10-11 | 6 | -0/+18 | |
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| * | | | | | | | UHD: reordered MIMO set_rx_bandwidth arg order | Nick Foster | 2010-10-11 | 2 | -2/+2 | |
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| * | | | | | | | UHD: Brought out set_rx_bandwidth for dboards with programmable rx filters. | Nick Foster | 2010-10-11 | 6 | -0/+18 | |
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* | | | | | | | Merge branch 'dbsrx_clock_div' | Josh Blum | 2010-10-11 | 1 | -10/+12 | |
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| * | | | | | | DBSRX: Fixed some ASSERT statements. | Nick Foster | 2010-10-11 | 1 | -8/+8 | |
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| * | | | | | | Fixed Assertions to better document tuning failures | Jason Abele | 2010-10-08 | 1 | -6/+8 | |
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* | | | | | | | uhd: fix async msg test to reflect new timeout api | Josh Blum | 2010-10-08 | 1 | -5/+3 | |
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* | | | | | | | TVRX documentation and a bugfix in the cal table. Named the antenna "RX". | Nick Foster | 2010-10-08 | 2 | -3/+12 | |
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* | | | | | | usrp: comments for set subdev spec in single usrp | Josh Blum | 2010-10-08 | 1 | -0/+10 | |
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* | | | | | | uhd: better warning message for failing to set rt priority | Josh Blum | 2010-10-08 | 1 | -1/+8 | |
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* | | | | | | usrp: added calls to get subdev and mboard canonical names | Josh Blum | 2010-10-08 | 2 | -6/+28 | |
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* | | | | | | tvrx: added enabled prop to set and get | Josh Blum | 2010-10-08 | 1 | -0/+8 | |
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* | | | | | | Merge branch 'subdev_enable' into next | Josh Blum | 2010-10-08 | 11 | -2/+115 | |
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| * | | | | | | usrp: added subdev enabled property | Josh Blum | 2010-09-30 | 11 | -2/+115 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | the dboard manager will disable all subdevs at startup and shutdown setting the subdev spec will enable only the subdevs in use all dboards are currently implemented as always enabled nothing tested | |||||
* | | | | | | | udp: add docs note about the udp transport | Josh Blum | 2010-10-08 | 1 | -0/+3 | |
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* | | | | | | | udp: worked blocking send back into udp transport, enable async with #define | Josh Blum | 2010-10-08 | 3 | -62/+99 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | tweaked some code in bounded buffer | |||||
* | | | | | | | udp: fix msvc errors for udp transport | Josh Blum | 2010-10-07 | 1 | -2/+2 | |
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* | | | | | | | udp: implementation for blocking recv w/ timeout, switch async ↵ | Josh Blum | 2010-10-07 | 1 | -39/+101 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | implementation w/ #define | |||||
* | | | | | | | tvrx: converted floats to doubles to avoid msvc warnings | Josh Blum | 2010-10-07 | 1 | -55/+55 | |
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* | | | | | | | uhd: tweaked docs/notes on transports | Josh Blum | 2010-10-07 | 1 | -2/+5 | |
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* | | | | | | | usrp1: ensure that the current buffer was committed before getting a new one | Josh Blum | 2010-10-07 | 1 | -1/+5 | |
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* | | | | | | | usrp2: moved samples per packet calculation into io_impl | Josh Blum | 2010-10-07 | 2 | -20/+22 | |
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* | | | | | | | usrp1: use the transport frame sizes to calculate the max spp | Josh Blum | 2010-10-06 | 2 | -80/+99 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The max send spp is the frame size minus the alignment padding. This allows us to copy a remainder into a new buffer and always commit multiples of the alignment size (512 bytes). Reworked the managed send buffer implementation to handle the above. Uses only managed memory, and only mem-copied under the alignment. | |||||
* | | | | | | | udp: fixed boost format syntax for warning message | Josh Blum | 2010-10-06 | 1 | -3/+3 | |
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