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* Merge branch 'fpga_ise12' into fpga_nextJosh Blum2010-11-230-0/+0
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| * no need for second sequence number anymore. Each dsp tx chainMatt Ettus2010-11-212-11/+8
| * shouldn't be executableMatt Ettus2010-11-201-0/+0
| * modernize the testbenchMatt Ettus2010-11-191-18/+30
| * get rid of extraneous U messages when we actually had an ACKMatt Ettus2010-11-182-7/+10
| * fix problem with consecutive timed packets on txMatt Ettus2010-11-181-2/+0
| * simplify time comparison to speed up logic and meet fpga timingMatt Ettus2010-11-132-4/+27
| * we're still on version 12.1Matt Ettus2010-11-132-2/+2
| * Add flow control and other small vrt fixes to u2p, minor cleanupsMatt Ettus2010-11-112-34/+38
| * reset properlyMatt Ettus2010-11-111-0/+1
| * compiles with new file locationsMatt Ettus2010-11-111-1/+1
| * handle zero-length packets properlyMatt Ettus2010-11-113-55/+76
| * clear out the vita tx chain and the tx fifo. need to check the fifoMatt Ettus2010-11-115-24/+25
| * added ability to truly clear out the entire rx chain. also removed old style...Matt Ettus2010-11-113-29/+27
| * gray code address for emiMatt Ettus2010-11-111-1/+7
| * fifo randomizer for emiMatt Ettus2010-11-115-4/+108
| * now handles frames larger than the vita packet (i.e. with padding)Matt Ettus2010-11-111-6/+16
| * don't clear out following packets on an eob ackMatt Ettus2010-11-111-1/+1
| * don't flag an error on eob ackMatt Ettus2010-11-111-1/+1
| * proper triggering for interrupts generated on the dsp_clkMatt Ettus2010-11-111-1/+8
| * cleanup for 32 bit seqnumMatt Ettus2010-11-111-4/+3
| * increase compatibility number for flow controlMatt Ettus2010-11-111-1/+1
| * switch to 32 bit sequence numbers. Will wrap in ~15 hours at max rateMatt Ettus2010-11-113-14/+16
| * send message on eob to ack the end of transmissionMatt Ettus2010-11-111-1/+6
| * typo which isn't caught by xilinxMatt Ettus2010-11-111-1/+1
| * separated flow control and error reporting on tx path. should work with and ...Matt Ettus2010-11-114-25/+43
| * go to the correct stateMatt Ettus2010-11-111-3/+3
| * add a fifo to the end of the mux to help in timing.Matt Ettus2010-11-111-6/+13
| * add trigger to makefileMatt Ettus2010-11-111-0/+1
| * assign setting reg addressesMatt Ettus2010-11-111-2/+2
| * declarationsMatt Ettus2010-11-111-2/+3
| * checkpoint in flow control packet generationMatt Ettus2010-11-115-42/+147
| * these got dropped during the rebaseMatt Ettus2010-11-114-31/+37
| * Removed 'ifdef for second DCM that was a deign idea for external SRAM on u2pl...Ian Buckley2010-11-111-49/+4
| * 1) Created new FIFO IP in Coregen. 512x36 dual clcok FIFO with programable fu...Ian Buckley2010-11-1111-11/+555
| * 1) u2p has added a new signal from the SRAM to the pinout, RAM_ZZIan Buckley2010-11-114-11/+17
| * Defaulted all SRAM pins to LVCMOS25 8mA FASTIan Buckley2010-11-111-67/+67
| * Placed 2nd DCM into `ifdef DCM_FOR_RAMCLK which is dissabled by defaultIan Buckley2010-11-112-7/+23
| * Added external RAM FIFO to u2plus.Ian Buckley2010-11-1120-100/+4498
| * revert unneeded changes and incorrect commentsMatt Ettus2010-11-112-34/+34
| * reconnect GPIOs, remove debug pins, meets timing nowMatt Ettus2010-11-111-5/+3
| * Modified phase shift of DCM1 to -64 which is intended to give more timing mar...Ian Buckley2010-11-111-1/+1
| * Enabled phase offset adjustment on DCM_INST1 which drives the external Fast S...Ian Buckley2010-11-111-12/+12
| * Added to DCM's and some BUFG's to align the internal 125MHz clock edge with i...Ian Buckley2010-11-114-5/+100
| * Enhanced test bench to be more like real world applicationIan Buckley2010-11-112-7/+14
| * hangedddddddextrnal fifo size to use full NoBL SRAMianb2010-11-111-1/+1
| * Corrected extfifo code so that all registers that are on SRAM signals are pac...ianb2010-11-115-46/+59
| * capacity logic fixMatt Ettus2010-11-111-1/+1
| * Added capacity to the module pinoutIan Buckley2010-11-111-3/+4
| * Added a bunch of debug signals.Ian Buckley2010-11-114-9/+19
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