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| * | | | | | uhd: windows fixes and formatting for hammer example | Josh Blum | 2012-03-30 | 1 | -293/+293 | |
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| * | | | | | Merge branch 'maint' | Josh Blum | 2012-03-29 | 7 | -5/+15 | |
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| | * | | | | usrp1: stop threads in deconstructor | Josh Blum | 2012-03-29 | 3 | -4/+10 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Its important to stop the threads before we let the other smart point objects naturally deconstruct to avoid thread-based race conditions. The attempt to deconstruct the tree and soft time ctrl had a bug because the tree had references in subtrees within the dboard manager class. Rather than continue to fix this method and deconstruct the tree to free up soft time ctrl, it seems simpler to just stop the thread in soft time ctrl, and then let it naturally deconstruct later by ref count. | |||||
| | * | | | | cmake: Binaries give notification before installing or uninstalling UHD. ↵ | Nicholas Corgan | 2012-03-29 | 4 | -1/+5 | |
| | |/ / / | | | | | | | | | | | | | | | | Better to give an output than just an empty pause. | |||||
| * | | | | examples: Transport Hammer - a stress test that calls for random or ↵ | Nicholas Corgan | 2012-03-27 | 2 | -0/+349 | |
| | | | | | | | | | | | | | | | | | | | | user-specified amounts of TX or RX samples with little to no delay between calls | |||||
* | | | | | Merge branch 'master' into next | Josh Blum | 2012-03-26 | 8 | -126/+169 | |
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| * | | | | Merge branch 'maint' | Josh Blum | 2012-03-26 | 2 | -4/+25 | |
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| | * | | | dbsrx: limit the USRP1 + DBSRX GPIO clock rate to 4MHz | Josh Blum | 2012-03-26 | 1 | -1/+8 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | This fixes the lockup/clocking condition when the following hw combo is used: USRP1 r4.5 + DBSRX + another i2c board | |||||
| | * | | | usrp2: possible fix for invalid broadcast replies | Josh Blum | 2012-03-26 | 1 | -3/+17 | |
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| * | | | | Merge branch 'maint' | Josh Blum | 2012-03-26 | 4 | -85/+92 | |
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| | * | | | Merge branch 'fpga_maint' into maint | Josh Blum | 2012-03-26 | 4 | -85/+92 | |
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| | | * | | B100: port cleanups from b100-txbug to this branch | Nick Foster | 2012-03-26 | 2 | -28/+21 | |
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| | | * | | fpga: fifo_2clock handles widths and sizes in-between corgens | Josh Blum | 2012-03-25 | 1 | -21/+23 | |
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| | | * | | b100: cleanup redundant logic for slwr and slrd | Josh Blum | 2012-03-25 | 1 | -2/+2 | |
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| | | * | | b100: extra data pktend cycle for fifo addr | Josh Blum | 2012-03-25 | 1 | -2/+8 | |
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| | | * | | b100: slave fifo fix for dst/src ready signals | Josh Blum | 2012-03-24 | 2 | -35/+41 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some of the changes my be overkill, but the idea is to be more careful about allowing FIFO IO to occur on transitions. The cal app was able to complete successfully. | |||||
| * | | | | fx2: simplify i2c code and overload eeprom read/write | Josh Blum | 2012-03-26 | 1 | -15/+24 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | Overload eeprom routines to do it in 1 transaction, since default will split it up into many for each byte. | |||||
| * | | | | Merge branch 'maint' | Josh Blum | 2012-03-26 | 1 | -22/+28 | |
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| | * | | | uhd: use release mode and git count for stable and unstable builds | Josh Blum | 2012-03-26 | 1 | -22/+28 | |
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* | | | | | Merge branch 'master' into next | Josh Blum | 2012-03-23 | 1 | -1/+1 | |
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| * | | | | Merge branch 'maint' | Josh Blum | 2012-03-23 | 1 | -1/+1 | |
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| | * | | | Changes preinst.in to 'echo' instead of 'ls' | Nicholas Corgan | 2012-03-23 | 1 | -1/+1 | |
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* | | | | | uhd: updated sync docs for timed commands | Josh Blum | 2012-03-23 | 1 | -1/+34 | |
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* | | | | | Merge branch 'fpga_next' into next | Josh Blum | 2012-03-23 | 12 | -426/+1454 | |
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| * | | | | spi core: ready logic low one cycle earlier | Josh Blum | 2012-03-16 | 1 | -1/+1 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | FIFO ctrl can poke registers every other cycle, the extra time to register not ready for spi core was too long. And it with ~trigger to get the not-ready one cycle earlier, so FIFO ctrl can block on the 2nd potential spi transaction. | |||||
| * | | | | fifo ctrl: parameterize having a proto header | Josh Blum | 2012-03-16 | 4 | -10/+12 | |
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| * | | | | fifo ctrl: rename fifo ctrl module and add sid ack param | Josh Blum | 2012-03-16 | 4 | -37/+40 | |
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| * | | | | fifo ctrl: minor fixes for spi core, swap time define | Josh Blum | 2012-03-16 | 5 | -10/+10 | |
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| * | | | | fifo ctrl: simplified perfs, added spi clock idle phase | Josh Blum | 2012-03-16 | 5 | -333/+341 | |
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| * | | | | fifo ctrl: minor fixes from last commit | Josh Blum | 2012-03-16 | 3 | -366/+366 | |
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| * | | | | fifo ctrl: spi core work, fifo ctrl perifs, usrp2 support | Josh Blum | 2012-03-16 | 5 | -370/+429 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Continued work on simple spi core. Added peripherals input to fifo ctrl so perifs can backpressure fifo ctrl. Copied the implementation into usrp2 core. | |||||
| * | | | | spi: created simple spi core (sr based) | Josh Blum | 2012-03-16 | 4 | -383/+593 | |
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| * | | | | fifo ctrl: simplified result packets (no tsf or sid) | Josh Blum | 2012-03-16 | 1 | -16/+7 | |
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| * | | | | fifo_ctrl: switched to medfifo and separate result fifo | Josh Blum | 2012-03-16 | 3 | -92/+122 | |
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| * | | | | fifo_ctrl: clear settings reg, and flow control | Josh Blum | 2012-03-16 | 3 | -10/+17 | |
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| * | | | | fifo ctrl: added time compare for timed commands | Josh Blum | 2012-03-16 | 1 | -3/+7 | |
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| * | | | | srb: created command queue, in and out state machines | Josh Blum | 2012-03-16 | 3 | -99/+162 | |
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| * | | | | usrp2: added vrt pack/unpacker to fifo ctrl | Josh Blum | 2012-03-16 | 1 | -40/+107 | |
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| * | | | | usrp2: first pass implementation of fifo control | Josh Blum | 2012-03-16 | 6 | -10/+594 | |
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* | | | | Merge branch 'master' into next | Josh Blum | 2012-03-23 | 1 | -3/+4 | |
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| * | | | Merge branch 'maint' | Josh Blum | 2012-03-23 | 1 | -3/+4 | |
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| | * | | usrp: fix for rx_frontend_core_200 dc offset | Josh Blum | 2012-03-23 | 1 | -3/+4 | |
| | | | | | | | | | | | | | | | | | | | | Mask off upper bits when setting a constant offset (I and Q regs). The sign bits (if negative) can flow off into the flags field. | |||||
* | | | | sbx: various fixes and tweaks for locking | Josh Blum | 2012-03-23 | 1 | -4/+3 | |
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* | | | | sbx: mods for PLL sync reset | Josh Blum | 2012-03-23 | 1 | -3/+6 | |
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* | | | | sbx: no readback during tuning, cache lock detect status when read | Josh Blum | 2012-03-23 | 4 | -12/+26 | |
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* | | | | fifo ctrl: code reorganization and integer wrap-around arithmetic | Josh Blum | 2012-03-23 | 1 | -65/+90 | |
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* | | | | fifo ctrl: implement timed command feature detection | Josh Blum | 2012-03-23 | 2 | -2/+12 | |
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* | | | | uhd: added setup sleep to tx waveforms | Josh Blum | 2012-03-23 | 1 | -1/+4 | |
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* | | | | fifo ctrl: use regular iface for U2_REG_MISC_CTRL_CLOCK | Josh Blum | 2012-03-23 | 2 | -6/+136 | |
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* | | | | fifo ctrl: various tweaks | Josh Blum | 2012-03-23 | 4 | -12/+14 | |
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