| Commit message (Collapse) | Author | Age | Files | Lines |
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created new component wb_readback_mux_16LE.v for 16 wide bus
connected vita time pps to vita time controller and readbacks
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Conflicts:
usrp2/top/u2_rev3/u2_core.v
usrp2/top/u2plus/u2plus_core.v
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underruns. There is a timeout so it won't go forever.
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a single buffer.
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without debug
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added stack start signal to zpu
removed wb perifs in n210 out of 0-16k
added reset controller for main app
rewire cpu addr line after booted use 0-16k
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Conflicts:
usrp2/top/u2_rev3/u2_core.v
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