| Commit message (Collapse) | Author | Age | Files | Lines |
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The old code used a non standard (though very common) way
to determine the size of an array.
In order to avoid warnings, pass another parameter to indicate
the size.
Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
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- u8: Converts arbitrary-length strings from and to item32
- item32->item32 memcpy non-conversion
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- Useful for tracking changes to a data type
- dirty_tracked serves as a wrapper for a data type with the changed flag embedded
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- Added get_register_info function to get bitwidth and R/W access for a registers
- Better error reporting
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- Added regmap object to soft_register library
- Added a regmap_db object to hold multiple regmaps/dbs
- Multiple soft_register enhancements
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Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
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This commit introduces the "gps_gpgga" sensor and exposes it via
the property tree.
Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
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This commit introduces the "gps_gprmc" sensor and exposes it via
the property tree.
Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
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The gpsd_iface class might be useful for more than just e3x0,
it therefore belongs into lib/usrp instead of lib/usrp/e300.
A new UHD component is being registered, to cope with the additional
dependency. If libgps is not found, UHD and E300 will be compiled
without GPS support.
This has several consequences:
- The E310 GPSDO should now work transparently over network
- Users can use the GPS through gpsd for other applications
*while* running UHD applications
- We now have a dependency on libgps
We need currently at least version 3.11 (while running 3.14),
on the device. Older versions do work if 3.10 runs on both
sides e.g
Reviewed-by: Martin Braun <martin.braun@ettus.com>
Reviewed-by: Ashish Chaudhari <ashish.chaudhari@ettus.com>
Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
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- Created AD936x manager class
- Moved functionality from B2x0 and E310 into manager
- Separated property tree + perifs initialization in both device classes
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UHD 3.8.5 increased the TX framesize from 2048 to 4096,
this can lead to issues in 2x2.
The behaviour can avoided by specifying send_frame_size = 2048
for these scenarios.
Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
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Firmware Revision 2.0 introduced the possibility to configure
the power on behavior.
This documents how to configure it through sysfs.
Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
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The fuses weren't written correctly before, as we were
lacking parameters to avrdude.
Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
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UHD 3.8.5 increased the TX framesize from 2048 to 4096,
this can lead to issues in 2x2.
The behaviour can avoided by specifying send_frame_size = 2048
for these scenarios.
Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
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- Delays changed after ADC config change and FPGA fixes
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- radio_rst was being asserted to reset the capture iface IDELAYs but
that was excessive and had adverse effects on the rest of the radio
- Replaced radio_rst with a localized IDELAYCTRL reset
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* Improved toolchan file, accounts for different versions
* Don't force static runtime linking (was causing test errors)
* Include MinGW runtime in packaging
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This reverts commit a12b24027fe1af9ca51949f6a9333ac5451690ef.
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- The following function implementations were moved from x300_impl.cpp
to x300_adc_dac_utils.cpp
- synchronize_dacs
- self_test_adcs
- extended_adc_test
- self_cal_adc_capture_delay
- self_cal_adc_xfer_delay
- This reduces the size of the x300_impl object file
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- We added additional microcode to configure DCI matching,config rate,etc
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- The value was originally empirically determined based on self-cal
results. After the fix for uncalibrated IDELAY, the self-cal offset
data was no longer correct.
- The new delay through the ADC ensures that the self-cal nominally
pick the halfway tap of 16
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- Everytime the LMK is configured, we do the following:
- Reset all LMK regs
- Wait for LMK lock
- Reset radio_clk PLL in FPGA
- Wait for FPGA PLL to lock
- Assert radio_rst which resets downstream radio logic
- This address the intermittent self-cal failures due to uncalibrated IDELAY taps
- Bumped FPGA compat to 12
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- This changed with the ADS62P44 -> ADS62P48 design change
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