| Commit message (Collapse) | Author | Age | Files | Lines |
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Fixup for last commit (9105f4fe) to update FPGA submodule.
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This fixes an issue where the git hash was not properly encoded in the
FPGA image.
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When running
$ n3xx_bist ddr3
The test will now load the AA image if the BIST fails, unless the user
specifies
$ n3xx_bist ddr3 -o skip_load_fpga=1
The rationale is that by default, the AA image is the only one that
includes the DmaFIFO block.
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The capability to run the DDR3 BIST is built into the DmaFIFO RFNoC
block, which is not always available. This change performs a quick check
before for its existence before retrieving the throughput values, and
thus can provide a better error message in that case.
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We can't guarantee that there is actually a DDR3/DRAM FIFO block on the
image. So, don't run that test by default.
In order to run the DDR3 bist, running `n3xx_bist ddr3` is still valid.
However, it requires an image with the DRAM FIFO enabled.
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Fixes uhd_usrp_probe FPGA version githash to report the
correct hash and not 'UNKNOWN'.
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Update N320 CPLD and N300/N310 AA images.
Signed-off-by: Michael West <michael.west@ettus.com>
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The previous zip file had accidentally archived the wrong images. This
provides the correct images. From uhd_usrp_probe:
- FPGA Version: 5.3
- FPGA git hash: 4bc2c6f.clean
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Without this patch, the N320 code will rely on an error to occur to
determine the non-existence of the N321 LO distribution board. While
this works, it forces an error message where there's no error. This will
first check for the existence of the board before trying to initialize
it.
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Remove "${prefix}/lib" from the DYLD path for APPLE only. Apple's DYLD
uses the paths embedded in the binary file (library or executable) as a
secondary means for finding referenced libraries. Explicitly including
"${prefix}/lib" can result in libraries being found and used by System
frameworks that are not compatible with them. Moving to just using build
paths fixes this issue.
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Hardware revision was increased due to new firmware. No software
changes are required.
Signed-off-by: michael-west <michael.west@ettus.com>
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The configure_flow_control_out function was set to dump any packets
onto the crossbar, which could cause issues on the crossbar and in
downstream blocks. Replacing wil a call to the _flush() function in
the block_ctrl_base parent class, which drops the packets so they do
not get put onto the crossbar.
Signed-off-by: Michael West <michael.west@ettus.com>
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FC ACK packets are unnecessary on lossless links and degrade overall
performance. This change disables those packets on all lossless links.
Signed-off-by: Michael West <michael.west@ettus.com>
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The RFNoC call set_rx_gain() would previously ignore the additional 6 dB
that can be set on the ADC. On the BasicRX board in particular, this
meant there was no RX gain setting at all.
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This change prevents invalid positional options from being accepted into
uhd_image_loader. Previously, if a user forgot to specify the option
type, uhd_image_loader would proceed and look like it succeeded, but the
intended image may not have been loaded.
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The link to the MPM page in the DPDK docs was incorrectly named. This
change links to the correct page name.
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Fixes issue where Doxygen doesn't recognize a block within N3XX's Salt
subsection as code.
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- expert_nodes.hpp: fix to work with BOOST_VERSION < 105600, since UHD
still supports Boost 1.53.00.
- gpio_atr_3000.hpp: requires boost::noncopyable header, so replicate
that (now) in export_nodes.hpp.
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Signed-off-by: michael-west <michael.west@ettus.com>
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Signed-off-by: michael-west <michael.west@ettus.com>
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- Update n3xx_common_* paths for 3.14.0.0
- Add N320 CPLD
Signed-off-by: michael-west <michael.west@ettus.com>
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- Updated CHANGELOG
- Updated fpga-src submodule
- Updated version info
- Updated manifest
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Issue: Current code loads FPGA too early while many
essential peripherals such as net clocks are not brought up.
This change will make sure those are got init before FPGA loaded.
Signed-off-by: Trung Tran<trung.tran@ettus.com>
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This commit adds FPGA functional verification tests for all the N320
images. The tests follow a similar pattern to N310, but one additional
category is present for using the DPDK transport. In order to use that
test, the use_dpdk and mgmt_addr args must be specified in the options.
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Eliminates errors during application shutdown by explicitly destroying
RFNoC blocks before loading the idle image.
Signed-off-by: michael-west <michael.west@ettus.com>
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Increase frame size from 364 to 508 samples. Reduces overhead. For
some reason yet to be understood, sizes over 508 do not work.
Signed-off-by: michael-west <michael.west@ettus.com>
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Fixes streaming on E310 after BBFC changes.
Signed-off-by: michael-west <michael.west@ettus.com>
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Limit number of unacknowledged control packets to the number of
receive frames in the transport to prevent the transport from
getting locked up or being overrun by ACK packets.
Signed-off-by: michael-west <michael.west@ettus.com>
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Signed-off-by: michael-west <michael.west@ettus.com>
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- Removed incorrect function call to set tick rate in
x300_radio_ctrl_impl.
- Modified legacy compat layer to properly set tick and sample rates.
These changes eliminate the tick and sample rate warnings during X300
initialization if TwinRX is used and allow for TwinRX to be used
alongside other types of daughterboards in the same X300.
Signed-off-by: michael-west <michael.west@ettus.com>
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Scale the M and N values if the tick_rate differs from the sample rate.
Fixes timestamps in packets when using TwinRX on X300.
Signed-off-by: michael-west <michael.west@ettus.com>
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Signed-off-by: michael-west <michael.west@ettus.com>
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- Store number of input and ouptput ports from block definition.
- Use number of input and ouptut ports for graph traversal rather
than number of connected blocks.
- Fixes DAC synchronization failure errors when using only one TX
channel on X300.
Signed-off-by: michael-west <michael.west@ettus.com>
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Avoid sending flow control ACK packets for lossless transports.
Add 'send_no_fc_acks' device argument to explicitly prevent
flow control ACK packets from being sent.
Signed-off-by: michael-west <michael.west@ettus.com>
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This doesn't add any functionality to the phase alignment script, but it
does make the siggen portion pluggable.
Co-authored-by: Brent Stapleton <brent.stapleton@ettus.com>
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This adds some info about what is happening in the dpdk_zero_copy
transport, especially the fact that there are threads spun off that take
over CPUs.
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Co-authored-by: Alex Williams <alex.williams@ni.com>
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update_component will reinit the device therefore we should use
MPMD_DEFAULT_INIT_TIMEOUT.
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Added explicit use of default block controller to remove warnings.
Signed-off-by: michael-west <michael.west@ettus.com>
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Signed-off-by: michael-west <michael.west@ettus.com>
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