| Commit message (Collapse) | Author | Age | Files | Lines |
|\ |
|
| |\ |
|
| | | |
|
| | | |
|
| | | |
|
| | | |
|
| |\|
| | |
| | |
| | |
| | | |
Conflicts:
host/lib/usrp/b200/b200_impl.cpp
|
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | | |
This will set the actual default rate to an integer factor
of whatever the tick rate is, but leave the property tree
value at zero. This avoids warnings if the chosen tick rate
is not a multiple of the previous default rate, but also
returns a zero value for the rate when it has not been
initialized, allowing the user to probe if the value has not
yet been set.
|
| | | |
|
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | | |
This will set the actual default rate to an integer factor
of whatever the tick rate is, but leave the property tree
value at zero. This avoids warnings if the chosen tick rate
is not a multiple of the previous default rate, but also
returns a zero value for the rate when it has not been
initialized, allowing the user to probe if the value has not
yet been set.
|
| |\| |
|
| | | |
|
| | | |
|
| | | |
|
| | | |
|
| | |
| | |
| | |
| | |
| | |
| | |
| | | |
- Self-calibration routine steps through various values of IDELAY
taps on the SS data bits to detect metastability in the capture interface
and computes an ideal delay tap value
- Self calibration is triggered at device creation
|
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | | |
- Self-calibration routine steps through various values of LMK
delay to detect metastability in the SSCLK -> radio_clk crossing
and computes an ideal delay for the ADC clock.
- Self calibration is triggered at startup if the self_cal_adc_delay
device arg is specified
|
| | |
| | |
| | |
| | |
| | |
| | |
| | | |
- This function allows delaying divider pairs using the digital and analog
delay blocks in the LMK divider
- ctrl object caches delay for later retrieval
- Minor fixes to LMK regmap
|
| | | |
|
| | | |
|
|/ / |
|
|\| |
|
| | |
|
| | |
|
| |
| |
| |
| |
| | |
* Use -DCUSTOM_RC_FILE=(filepath) option to use custom RC file
* Defaults to host/lib/uhd.rc.in if none specified
|
|\| |
|
| | |
|
| | |
|
|\|
| |
| |
| |
| | |
Conflicts:
host/include/uhd/usrp/multi_usrp.hpp
|
| | |
|
|\|
| |
| |
| |
| |
| |
| | |
Conflicts:
host/lib/usrp/common/ad9361_ctrl.hpp
host/lib/usrp/common/ad9361_driver/ad9361_device.h
host/lib/usrp/e300/e300_remote_codec_ctrl.hpp
|
| | |
|
| | |
|
| |
| |
| |
| | |
When the LO is tuned it changes the frequency on both channels. The frequency value read back for the first channel was not updated when the LO frequency for the other channel was tuned to a different value.
|
| | |
|
| | |
|
| |
| |
| |
| | |
Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
|
| |
| |
| |
| | |
Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
|
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| | |
The sc16-sc16 wire to host type converter is effectively an I/Q swap
or 16-bit byteswap for little and big endian cases respectively. This
implmentation is a subset of fc32 and fc64 converters without the
floating point portion and scaling.
The resulting byte ordering is as follows:
-----------------
| A | B | C | D | Wire
-----------------
0 1 2 3
-----------------
| C | D | A | B | Litte-endian
-----------------
0 1 2 3
-----------------
| B | A | D | C | Big-endian
-----------------
0 1 2 3
Signed-off-by: Tom Tsou <tom.tsou@ettus.com>
|
| |
| |
| |
| | |
Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
|
| |
| |
| |
| | |
Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
|
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| | |
The sc16-sc16 wire to host type converter is effectively an I/Q swap
or 16-bit byteswap for little and big endian cases respectively. This
implmentation is a subset of fc32 and fc64 converters without the
floating point portion and scaling.
The resulting byte ordering is as follows:
-----------------
| A | B | C | D | Wire
-----------------
0 1 2 3
-----------------
| C | D | A | B | Litte-endian
-----------------
0 1 2 3
-----------------
| B | A | D | C | Big-endian
-----------------
0 1 2 3
Signed-off-by: Tom Tsou <tom.tsou@ettus.com>
|
| | |
|
| | |
|
|\|
| |
| |
| |
| |
| |
| | |
Conflicts:
fpga-src
host/CMakeLists.txt
host/cmake/Modules/UHDVersion.cmake
|
| | |
|
| | |
|
| |
| |
| |
| |
| |
| | |
- Updated fpga-src
- Updated version strings
- Updated images package
|
| |
| |
| |
| |
| | |
Max rate is now set to 53248000, allowing for more than 8MS/s,
which is closer to the actual value that USB2 can handle.
|
| | |
|