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* fpga: sim: Check for empty packet in clear_unused_bytesWade Fife2021-06-171-0/+4
* x400: sim: Move testbenches to sim folderWade Fife2021-06-1713-0/+0
* fpga: Update testbenches to work in ModelSimWade Fife2021-06-1711-136/+303
* fpga: x400: Add makefiles for RF testbenchesWade Fife2021-06-177-3/+212
* fpga: tools: Detect assertions in ModelSim simulationWade Fife2021-06-171-2/+22
* fpga: tools: Put SIM_SRCS at end of compile orderWade Fife2021-06-171-1/+1
* fpga: tools: Support new FPGA types in viv_simulator.makWade Fife2021-06-171-2/+2
* fpga: tools: Fix python2 reference in viv_ip_builder.makWade Fife2021-06-171-1/+1
* fpga: tools: Add modelsim.excludesWade Fife2021-06-171-0/+18
* fpga: tools: Add modelsim.ini to ModelSim callsWade Fife2021-06-174-7/+38
* fpga: tools: Add features to run_testbenches.pyWade Fife2021-06-171-6/+19
* fpga: tools: Add ip target to simulation makefilesWade Fife2021-06-172-2/+6
* uhd: Update versionAaron Rossetto2021-06-161-1/+1
* docs: zbx: improve cpld update docsMichael Auchter2021-06-161-7/+5
* docs: usrp_x4xx: improve mb cpld update docsMichael Auchter2021-06-161-3/+2
* mpm: install cpld update scripts in runtime dirMichael Auchter2021-06-161-0/+10
* mpm: x4xx_bist: run spi_flash tests on both DBsMichael Auchter2021-06-151-9/+29
* uhd: x400: Honor ENABLE_X400 component flagAaron Rossetto2021-06-151-9/+14
* images: Update manifestAaron Rossetto2021-06-111-12/+12
* mpm: max10_cpld_flash_ctrl: only reprogram cpld if necessaryMichael Auchter2021-06-101-0/+8
* uhd: ci: Add test definition for UHD CIJoerg Hofrichter2021-06-105-2/+449
* uhd: Add support for the USRP X410Lars Amsel2021-06-10185-160/+61559
* images: add X410 series FPGA imagesJoerg Hofrichter2021-06-101-0/+6
* fpga: tools: Add X410 support for image packagingHumberto Jimenez2021-06-101-0/+24
* fpga: ci: Add build definitions for FPGA CIWade Fife2021-06-107-0/+483
* fpga: x400: zbx: Add support for ZBX CPLDJavier Valenzuela2021-06-1037-0/+17727
* fpga: x400: cpld: Add support for X410 motherboard CPLDMax Köhler2021-06-1042-0/+8377
* fpga: x400: Add support for X410 motherboard FPGAWade Fife2021-06-10207-1/+299667
* fpga: sim: Add slave_idle() to PkgAxiStreamBfm.svWade Fife2021-06-101-0/+4
* fpga: lib: Update register comments in eth_regs.vhWade Fife2021-06-101-1/+5
* fpga: Update rfnoc_image_core for all targetsWade Fife2021-06-1018-5780/+6492
* fpga: Update recommended HDL header guidelineWade Fife2021-06-101-0/+3
* transport: Set mtu to 9000 for all 10GbE use casesmattprost2021-06-103-8/+8
* fpga: tools: Fix part selection in setupenvSam O'Brien2021-06-101-4/+12
* cal: Add min_freq and max_freq attributes to USRPCalibratorBaseMartin Braun2021-06-101-2/+4
* cal: Fix minor issues in the calibration utilitiesMartin Braun2021-06-104-14/+15
* devtest: benchmark_rate: Add support for rx and tx only testsmattprost2021-06-101-19/+27
* multi_usrp: Factor out make_overall_tune_range() and fix limitsMartin Braun2021-06-093-42/+39
* mpmd: support four linksAndrew Lynch2021-06-082-0/+10
* fpga: Change RFNoC YAML version numbers to stringsWade Fife2021-06-0834-68/+68
* images: Update manifestAaron Rossetto2021-06-081-8/+8
* dboard_iface: Fix sleep()michael-west2021-06-031-1/+1
* rfnoc: Fix post action behavior of nodesLars Amsel2021-06-031-0/+4
* fpga: lib: Add modports to SV AXI-Stream blocksWade Fife2021-06-034-8/+8
* fpga: lib: Add time_increment port to timekeeperWade Fife2021-06-031-17/+43
* fpga: lib: Pipeline ctrlport_timerWade Fife2021-06-031-24/+81
* fpga: lib: Add clock domain comments to interfacesWade Fife2021-06-037-13/+28
* fpga: lib: Add 2 to 1 gearbox moduleWade Fife2021-06-035-0/+517
* fpga: lib: Add PHASE parameter to sim_clk_genWade Fife2021-06-031-1/+3
* fpga: lib: Add AXI4 (full) interfaceAndrew Moch2021-06-034-0/+619
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