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* Merge branch 'master' into flow_ctrlJosh Blum2010-10-2133-718/+2166
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| * usrp: remove irrelevant copied comment from single usrpJosh Blum2010-10-211-2/+0
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| * usrp: use a dash as the gain name prefix separator, removed RX/TX auto ↵Josh Blum2010-10-202-4/+4
| | | | | | | | suffix for XCVR board cnames
| * usrp: convenience wrappers for dealing with overall gainsJosh Blum2010-10-202-26/+66
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| * usrp: use the dboard id to prefix the subdev gain group namesJosh Blum2010-10-2010-32/+46
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| * usrp: added gain element access by gain name to multi and single wrappersJosh Blum2010-10-204-56/+150
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| * uhd: added name parameter to gain group, get range, set/get value by nameJosh Blum2010-10-204-18/+59
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| * usrp: added docstrings to single and multi usrp for undocumented methodsJosh Blum2010-10-202-4/+432
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| * usrp: updated docs to reflect switch to multi-usrp interfaceJosh Blum2010-10-192-5/+5
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| * uhd: remove some warnings in MSVC and with typo in xcvr2450Josh Blum2010-10-192-3/+4
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| * usrp: change the bandwidth param to a double (its a frequency), add set and ↵Josh Blum2010-10-196-34/+60
| | | | | | | | gets for BW in the wrappers
| * Merge branch 'multi_usrp'Josh Blum2010-10-1911-597/+1328
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| | * multi-usrp: fixed num channel calculation, moved logic to cpm functionsJosh Blum2010-10-191-16/+16
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| | * multi-usrp: corrected calculations for channel and mboard indexesJosh Blum2010-10-181-30/+25
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| | * usrp: deleted deprecated simple and mimo wrappers, moved implementations ↵Josh Blum2010-10-185-585/+557
| | | | | | | | | | | | into headers
| | * usrp: moved warnings logic into wrappersJosh Blum2010-10-174-18/+97
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| | * usrp: created multi-usrp (multi chan, multi board), and deprecated mimo-usrpJosh Blum2010-10-168-9/+694
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| * | uhd: split unit tests into individual tests by file + they get installedJosh Blum2010-10-192-7/+13
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| * | uhd: made ticks signed in time spec, fixed full secs implementation, added ↵Josh Blum2010-10-194-9/+78
| |/ | | | | | | unit tests
* | Merge branch 'master' into flow_ctrlJosh Blum2010-10-181-1/+1
|\| | | | | | | | | Conflicts: host/lib/usrp/usrp2/io_impl.cpp
| * usrp2: make the booty smaller than the number of recv framesJosh Blum2010-10-161-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This may fix some of our woes when the host cannot keep up. That is, with a smaller booty, the managed buffers will get freed up and the call to get buffer will never block waiting for a buffer to become free. This has several side effects: 1) Overflows are more likely to occur in the pirate thread. Pirate-based overflows will overwrite old packets, whereas socket-based overflows will discard newer incoming packets. 2) The pirate thread will continue to pull in async packets rather than loosing them in a socket-based overflow.
* | usrp2: dont need to start streaming for this hackJosh Blum2010-10-151-1/+0
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* | usrp2: temp fix to send dummy packets and flush so FPGA vita machine are in ↵Josh Blum2010-10-151-0/+26
| | | | | | | | known state
* | Merge branch 'flow_ctrl_with_fpga'Josh Blum2010-10-1577-405/+11159
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| * Merge branch 'flow_control' into flow_ctrlJosh Blum2010-10-1457-256/+10817
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| | * now handles frames larger than the vita packet (i.e. with padding)Matt Ettus2010-10-121-6/+16
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| | * don't clear out following packets on an eob ackMatt Ettus2010-10-121-1/+1
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| | * don't flag an error on eob ackMatt Ettus2010-10-121-1/+1
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| | * proper triggering for interrupts generated on the dsp_clkMatt Ettus2010-10-121-1/+8
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| | * cleanup for 32 bit seqnumMatt Ettus2010-10-111-4/+3
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| | * increase compatibility number for flow controlMatt Ettus2010-10-111-1/+1
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| | * switch to 32 bit sequence numbers. Will wrap in ~15 hours at max rateMatt Ettus2010-10-113-14/+16
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| | * send message on eob to ack the end of transmissionMatt Ettus2010-10-111-1/+6
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| | * typo which isn't caught by xilinxMatt Ettus2010-10-111-1/+1
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| | * separated flow control and error reporting on tx path. should work with and ↵Matt Ettus2010-10-104-25/+43
| | | | | | | | | | | | without flow control
| | * go to the correct stateMatt Ettus2010-10-081-3/+3
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| | * add a fifo to the end of the mux to help in timing.Matt Ettus2010-10-081-6/+13
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| | * add trigger to makefileMatt Ettus2010-10-081-0/+1
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| | * assign setting reg addressesMatt Ettus2010-10-081-2/+2
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| | * declarationsMatt Ettus2010-10-081-2/+3
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| | * checkpoint in flow control packet generationMatt Ettus2010-10-085-42/+147
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| | * revert unneeded changes and incorrect commentsMatt Ettus2010-10-073-38/+38
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| | * reconnect GPIOs, remove debug pins, meets timing nowMatt Ettus2010-10-061-5/+3
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| | * Merge branch 'ise12' into efifo_merge_dcmMatt Ettus2010-10-063-29/+23
| | |\ | | | | | | | | | | | | | | | | | | | | | | | | * ise12: fix timing problem on DAC output bus clean up DAC inversion and swapping to match schematics Clean up iq swapping on RX. It is now swapped in the top level. widened muxes to 4 bits to match tx side and handle more ADCs in future
| | | * fix timing problem on DAC output busMatt Ettus2010-10-011-2/+2
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| | * | Modified phase shift of DCM1 to -64 which is intended to give more timing ↵Ian Buckley2010-09-301-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | margin on reads from the SRAM at the expense of Writes to the SRAM. Tested to be at least as stable as a phase shift of 12 and beter looking timing on the logic analyzer. Signals driven by the FPGA are observed changing on the SRAM pins about 4 nS after the rising edge of the RAM clock.
| | * | Enabled phase offset adjustment on DCM_INST1 which drives the external Fast ↵Ian Buckley2010-09-141-12/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SRAM clock. Set phase shift to -12 after experimentation using logic analyzer to see results. This value gives near optimum 1.5nS setup times on the source sync signals FPGA -> SRAM under lab conditions.
| | * | Added to DCM's and some BUFG's to align the internal 125MHz clock edge with ↵Ian Buckley2010-09-014-5/+101
| | | | | | | | | | | | | | | | | | | | | | | | | | | | its presentation externally at the NoBL SRAM. Since we don't have a board level trace to use to estimate clock propigation delay we just loop through the I/O on the FPGA. This hasn't been verified as working on a USRP2 yet.
| | * | Merge branch 'efifo_merge' of git@ettus.sourcerepo.com:ettus/fpgapriv into ↵Ian Buckley2010-09-015-47/+60
| | |\ \ | | | | | | | | | | | | | | | efifo_merge
| | | * | hangedddddddextrnal fifo size to use full NoBL SRAMianb2010-08-251-1/+1
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