| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | fifo ctrl: spi core work, fifo ctrl perifs, usrp2 support | Josh Blum | 2012-03-16 | 5 | -370/+429 |
| * | spi: created simple spi core (sr based) | Josh Blum | 2012-03-16 | 4 | -383/+593 |
| * | fifo ctrl: simplified result packets (no tsf or sid) | Josh Blum | 2012-03-16 | 1 | -16/+7 |
| * | fifo_ctrl: switched to medfifo and separate result fifo | Josh Blum | 2012-03-16 | 3 | -92/+122 |
| * | fifo_ctrl: clear settings reg, and flow control | Josh Blum | 2012-03-16 | 3 | -10/+17 |
| * | fifo ctrl: added time compare for timed commands | Josh Blum | 2012-03-16 | 1 | -3/+7 |
| * | srb: created command queue, in and out state machines | Josh Blum | 2012-03-16 | 3 | -99/+162 |
| * | usrp2: added vrt pack/unpacker to fifo ctrl | Josh Blum | 2012-03-16 | 1 | -40/+107 |
| * | usrp2: first pass implementation of fifo control | Josh Blum | 2012-03-16 | 6 | -10/+594 |
| * | fpga: force -include_global for custom sources | Josh Blum | 2012-03-12 | 9 | -13/+16 |
| * | fpga: fix custom defs in some top level makefiles | Josh Blum | 2012-03-08 | 4 | -101/+3 |
| * | usrp2/nseries: added churn to meet timing | Josh Blum | 2012-02-18 | 2 | -2/+4 |
| * | vita rx: trigger clear after packet tranfer | Josh Blum | 2012-02-18 | 1 | -2/+22 |
| * | dsp rework: fix dspengine_8to16 to handle padded packets | Josh Blum | 2012-02-17 | 1 | -4/+3 |
| * | dsp_engine: fix for upper/lower swap, and odd length packets | Matt Ettus | 2012-02-16 | 1 | -16/+20 |
| * | dsp rework: added flusher to vita tx chain on clear | Josh Blum | 2012-02-15 | 1 | -8/+16 |
| * | dsp rework: minor simplification in vita_tx_deframer | Josh Blum | 2012-02-13 | 1 | -4/+1 |
| * | dsp rework: full-rate pipelining in vita tx deframer | Josh Blum | 2012-02-12 | 1 | -37/+51 |
| * | dsp rework: pass enables into glue, update power trig, parameterize, fix modu... | Josh Blum | 2012-02-10 | 9 | -103/+145 |
| * | dsp rework: implement 64 bit ticks no seconds | Josh Blum | 2012-02-06 | 10 | -111/+57 |
| * | B100: External FPGA reset from FX2 reuses fpga_cfg_cclk. | Nick Foster | 2012-02-06 | 2 | -2/+6 |
| * | dsp rework: pass vita clears into dsp modules, unified fifo clears | Josh Blum | 2012-02-04 | 14 | -81/+76 |
| * | b100: timing constraints on GPIF lines | Josh Blum | 2012-02-04 | 1 | -0/+9 |
| * | b100: connect all clears for gpif | Josh Blum | 2012-02-03 | 3 | -15/+8 |
| * | power_trig: test code for power trigger | Matt Ettus | 2012-02-02 | 1 | -0/+71 |
| * | dsp rework: rehash of the custom module stuff and readme | Josh Blum | 2012-02-02 | 26 | -262/+544 |
| * | power_trig: first cut at power trigger with fixed delay | Matt Ettus | 2012-02-02 | 2 | -2/+115 |
| * | dsp_rework: testbench enhancements | Matt Ettus | 2012-02-02 | 1 | -11/+34 |
| * | dsp rework: custom engine module for rx/tx vita chain | Josh Blum | 2012-02-01 | 13 | -138/+294 |
| * | dsp rework: register the sample in vita tx ctrl | Josh Blum | 2012-02-01 | 1 | -2/+11 |
| * | Merge branch 'slave_fifo_rebase' into dsp_rework | Josh Blum | 2012-02-01 | 6 | -35/+509 |
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| | * | Fix missing B100 core_compile (poor Git hygeine) | Nick Foster | 2012-01-23 | 1 | -0/+1 |
| | * | b100: bumped fpga compat number for slave fifo mode | Josh Blum | 2012-01-12 | 1 | -1/+1 |
| | * | Slave FIFO: fix for PKTEND not asserting @ end of RX. | Nick Foster | 2012-01-12 | 1 | -8/+8 |
| | * | B100: moar buffering on TX for better performance in bidirectional applications | Nick Foster | 2012-01-12 | 2 | -5/+5 |
| | * | Squashed slave mode changes onto master. | Nick Foster | 2012-01-12 | 7 | -34/+507 |
| * | | dsp rework: paramaterize post_engine_buffering | Josh Blum | 2012-02-01 | 3 | -4/+16 |
| * | | dsp_rework: handle longer headers | Matt Ettus | 2012-01-31 | 1 | -2/+8 |
| * | | dsp_rework: more thorough test | Matt Ettus | 2012-01-31 | 1 | -8/+20 |
| * | | dsp rework: finished engine HEADER_OFFSET stuff, add post_engine_buffering | Josh Blum | 2012-01-30 | 2 | -8/+13 |
| * | | dsp rework: work on 8 to 16 engine (usrp2 ok) | Josh Blum | 2012-01-30 | 2 | -25/+26 |
| * | | dsp_engine: work with transport header | Matt Ettus | 2012-01-30 | 1 | -16/+14 |
| * | | dsp rework: integrated dspengine_8to16, some tweaks | Josh Blum | 2012-01-30 | 3 | -8/+8 |
| * | | dsp: 8 to 16 bit conversion for tx side. believed to be functional | Matt Ettus | 2012-01-29 | 2 | -12/+230 |
| * | | dsp rework: increase the number of effective bits in the duc scale factor | Josh Blum | 2012-01-28 | 1 | -1/+1 |
| * | | dsp rework: added double buffer interface to vita tx | Josh Blum | 2012-01-28 | 5 | -12/+41 |
| * | | dsp rework: moved scale and round into ddc chain | Josh Blum | 2012-01-28 | 7 | -41/+49 |
| * | | dsp rework: top level fixes B100/E100 | Josh Blum | 2012-01-27 | 4 | -8/+9 |
| * | | dsp rework: integrated custom dsp module shells | Josh Blum | 2012-01-27 | 18 | -38/+370 |
| * | | dsp rework: implemented dsp changes for other top levels | Josh Blum | 2012-01-27 | 10 | -106/+203 |
