| Commit message (Collapse) | Author | Age | Files | Lines |
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without debug
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added stack start signal to zpu
removed wb perifs in n210 out of 0-16k
added reset controller for main app
rewire cpu addr line after booted use 0-16k
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Conflicts:
usrp2/top/u2_rev3/u2_core.v
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Conflicts:
usrp2/top/u2_rev3/Makefile
usrp2/top/u2_rev3/u2_core.v
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to sync on the received side.
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* time_compare_speedup:
should safely delay the late signal which was causing timing problems
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udp_wrapper in top level with some fifo conversion stuff
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module
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packet router to be muxed to com out
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inspector check
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in crossbar input)
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cpu, dsp, crs
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