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* udp_ports: fixed address comparison B+14 is comparisonJosh Blum2010-12-211-1/+1
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* don't overwrite checksum valuesMatt Ettus2010-12-211-7/+8
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* udp_ports: set the source port and destination port from tableJosh Blum2010-12-171-12/+16
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* generate port number headers in the dsp error unitsMatt Ettus2010-12-154-8/+12
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* now supports up to 4 different udp portsMatt Ettus2010-12-152-23/+43
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* time sync on usrp2 as well, added debug pins to time sync.Matt Ettus2010-12-102-2/+10
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* slave side can now syncMatt Ettus2010-12-102-13/+33
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* Only do udp now, renamed old ports to exp_time_*Matt Ettus2010-12-092-2/+2
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* udp is now the defaultMatt Ettus2010-12-092-2/+2
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* remove old raw ethernet versionMatt Ettus2010-12-092-882/+0
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* reimplemented mimo time transfer to handle 64 bits. Still needsMatt Ettus2010-12-095-71/+164
| | | | to sync on the received side.
* renamed exp_pps_* to be exp_time_*, which is the mimo synchronization signalMatt Ettus2010-12-095-22/+22
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* Merge branch 'time_compare_speedup' into ise12Matt Ettus2010-12-091-2/+16
|\ | | | | | | | | * time_compare_speedup: should safely delay the late signal which was causing timing problems
| * should safely delay the late signal which was causing timing problemsMatt Ettus2010-12-061-2/+16
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* | u2plus: clock lock pin capitalization failNick Foster2010-12-062-2/+2
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* packets are shorter now, so we need to tell the udp state machine that...Matt Ettus2010-11-231-1/+1
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* no need for second sequence number anymore. Each dsp tx chainMatt Ettus2010-11-212-11/+8
| | | | generates its own flow control packets now.
* shouldn't be executableMatt Ettus2010-11-201-0/+0
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* modernize the testbenchMatt Ettus2010-11-191-18/+30
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* get rid of extraneous U messages when we actually had an ACKMatt Ettus2010-11-182-7/+10
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* fix problem with consecutive timed packets on txMatt Ettus2010-11-181-2/+0
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* simplify time comparison to speed up logic and meet fpga timingMatt Ettus2010-11-132-4/+27
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* we're still on version 12.1Matt Ettus2010-11-132-2/+2
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* Add flow control and other small vrt fixes to u2p, minor cleanupsMatt Ettus2010-11-112-34/+38
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* reset properlyMatt Ettus2010-11-111-0/+1
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* compiles with new file locationsMatt Ettus2010-11-111-1/+1
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* handle zero-length packets properlyMatt Ettus2010-11-113-55/+76
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* clear out the vita tx chain and the tx fifo. need to check the fifoMatt Ettus2010-11-115-24/+25
| | | | reset to make sure it is in the correct clock domain.
* added ability to truly clear out the entire rx chain. also removed old ↵Matt Ettus2010-11-113-29/+27
| | | | style fifo in rx.
* gray code address for emiMatt Ettus2010-11-111-1/+7
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* fifo randomizer for emiMatt Ettus2010-11-115-4/+108
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* now handles frames larger than the vita packet (i.e. with padding)Matt Ettus2010-11-111-6/+16
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* don't clear out following packets on an eob ackMatt Ettus2010-11-111-1/+1
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* don't flag an error on eob ackMatt Ettus2010-11-111-1/+1
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* proper triggering for interrupts generated on the dsp_clkMatt Ettus2010-11-111-1/+8
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* cleanup for 32 bit seqnumMatt Ettus2010-11-111-4/+3
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* increase compatibility number for flow controlMatt Ettus2010-11-111-1/+1
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* switch to 32 bit sequence numbers. Will wrap in ~15 hours at max rateMatt Ettus2010-11-113-14/+16
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* send message on eob to ack the end of transmissionMatt Ettus2010-11-111-1/+6
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* typo which isn't caught by xilinxMatt Ettus2010-11-111-1/+1
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* separated flow control and error reporting on tx path. should work with and ↵Matt Ettus2010-11-114-25/+43
| | | | without flow control
* go to the correct stateMatt Ettus2010-11-111-3/+3
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* add a fifo to the end of the mux to help in timing.Matt Ettus2010-11-111-6/+13
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* add trigger to makefileMatt Ettus2010-11-111-0/+1
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* assign setting reg addressesMatt Ettus2010-11-111-2/+2
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* declarationsMatt Ettus2010-11-111-2/+3
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* checkpoint in flow control packet generationMatt Ettus2010-11-115-42/+147
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* these got dropped during the rebaseMatt Ettus2010-11-114-31/+37
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* Removed 'ifdef for second DCM that was a deign idea for external SRAM on ↵Ian Buckley2010-11-111-49/+4
| | | | | | u2plus. Hardcoded -90 degree clcok from first DCM as final solution
* 1) Created new FIFO IP in Coregen. 512x36 dual clcok FIFO with programable ↵Ian Buckley2010-11-1111-11/+555
| | | | | | full watermark 2) Put larger FIFO on output of u2plus extramfifo that is compatable with u2_rev3 EMI fixes.
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