Commit message (Collapse) | Author | Age | Files | Lines | |
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* | usrp2: removed unused memory map entries | Josh Blum | 2012-02-27 | 1 | -5/+1 |
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* | usrp1: fix to use the db connection type to determine DAC sign | Josh Blum | 2012-02-24 | 1 | -2/+10 |
| | | | | | | | | Unlike the other products, usrp1 uses the DAC and not DSP to perform baseband frequency shifting in the hardware. Therefore this shifting occurs before I and Q swapping, and so, the sign of the frequency needs to be inverted on daughterboards which have inverted I and Q TX inputs. | ||||
* | usrp1: fix advertised samples per packet in send streamer | Josh Blum | 2012-02-21 | 1 | -1/+2 |
| | | | | | Must subtract off the 511 for 512 modulus remainder commit. This bug was introduced by the conversion to streamer API. | ||||
* | Try really hard to get cmake to use compiler flags from the toolchain file. | Philip Balister | 2012-02-21 | 1 | -2/+2 |
| | | | | | | | | | | | | See: http://www.mail-archive.com/cmake@cmake.org/msg33248.html Also credit to OpenEmbedded for doing something similar in the toolchain file they create. Note that adding the SYSTEM_NAME to the toolchain file sets CROSS_COMPILING, which is not what we want for native compiling. Signed-off-by: Philip Balister <philip@opensdr.com> | ||||
* | usb: added /opt/local to libusb search path | Josh Blum | 2012-02-21 | 1 | -1/+2 |
| | | | | For OSX from MLD | ||||
* | usrp2: some tweaks to the device locking logic | Josh Blum | 2012-02-20 | 1 | -6/+9 |
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* | usrp2: added retry logic to control packets | Josh Blum | 2012-02-20 | 1 | -2/+32 |
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* | usrp2: changed download url for dd.exe | Josh Blum | 2012-02-18 | 2 | -2/+2 |
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* | Merge branch 'fpga_master' | Josh Blum | 2012-02-18 | 3 | -4/+26 |
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| * | usrp2/nseries: added churn to meet timing | Josh Blum | 2012-02-18 | 2 | -2/+4 |
| | | | | | | | | | | Added churn to readback mux on nseries to make n200r4 meet timing. Also added churn to usrp2 for parallelism, but assigned to zero. | ||||
| * | vita rx: trigger clear after packet tranfer | Josh Blum | 2012-02-18 | 1 | -2/+22 |
| | | | | | | | | | | | | | | To avoid blocking conditions down the pipe, avoid clearing vita rx during packet transfer. Adds state machine to delay the clear until after xfer completes. | ||||
* | | uhd: added -fvisibility-inlines-hidden | Josh Blum | 2012-02-18 | 1 | -1/+2 |
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* | | Merge branch 'next' | Josh Blum | 2012-02-17 | 123 | -1729/+3954 |
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| * | | Merge branch 'fpga_next' into next | Josh Blum | 2012-02-17 | 54 | -1070/+2565 |
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| | * | dsp rework: fix dspengine_8to16 to handle padded packets | Josh Blum | 2012-02-17 | 1 | -4/+3 |
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| | * | dsp_engine: fix for upper/lower swap, and odd length packets | Matt Ettus | 2012-02-16 | 1 | -16/+20 |
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| | * | dsp rework: added flusher to vita tx chain on clear | Josh Blum | 2012-02-15 | 1 | -8/+16 |
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| | * | dsp rework: minor simplification in vita_tx_deframer | Josh Blum | 2012-02-13 | 1 | -4/+1 |
| | | | | | | | | | | | | all n-series devices meet timing | ||||
| | * | dsp rework: full-rate pipelining in vita tx deframer | Josh Blum | 2012-02-12 | 1 | -37/+51 |
| | | | | | | | | | | | | | | | | | | | | | | | | The vita tx deframer can now pass payload at clock rate. This enables TX streaming at interpolations factors of 2. The vector capabilities of TX deframer have been kept in-tact, and should be functional, however, only MAXCHAN=1 has been tested. | ||||
| | * | dsp rework: pass enables into glue, update power trig, parameterize, fix ↵ | Josh Blum | 2012-02-10 | 9 | -103/+145 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | module inc DSP enables now pass through the glue and custom modules so it can be user-controlled. Updated power trigger to current spec, and added comments Pass width from dsp into glue, and use width to parameterize wires Fix custom module includes so they will build | ||||
| | * | dsp rework: implement 64 bit ticks no seconds | Josh Blum | 2012-02-06 | 10 | -111/+57 |
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| | * | B100: External FPGA reset from FX2 reuses fpga_cfg_cclk. | Nick Foster | 2012-02-06 | 2 | -2/+6 |
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| | * | dsp rework: pass vita clears into dsp modules, unified fifo clears | Josh Blum | 2012-02-04 | 14 | -81/+76 |
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| | * | b100: timing constraints on GPIF lines | Josh Blum | 2012-02-04 | 1 | -0/+9 |
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| | * | b100: connect all clears for gpif | Josh Blum | 2012-02-03 | 3 | -15/+8 |
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| | * | power_trig: test code for power trigger | Matt Ettus | 2012-02-02 | 1 | -0/+71 |
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| | * | dsp rework: rehash of the custom module stuff and readme | Josh Blum | 2012-02-02 | 26 | -262/+544 |
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| | * | power_trig: first cut at power trigger with fixed delay | Matt Ettus | 2012-02-02 | 2 | -2/+115 |
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| | * | dsp_rework: testbench enhancements | Matt Ettus | 2012-02-02 | 1 | -11/+34 |
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| | * | dsp rework: custom engine module for rx/tx vita chain | Josh Blum | 2012-02-01 | 13 | -138/+294 |
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| | * | dsp rework: register the sample in vita tx ctrl | Josh Blum | 2012-02-01 | 1 | -2/+11 |
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| | * | Merge branch 'slave_fifo_rebase' into dsp_rework | Josh Blum | 2012-02-01 | 6 | -35/+509 |
| | |\ | | | | | | | | | | | | | | | | | Conflicts: usrp2/top/B100/u1plus_core.v | ||||
| | | * | Fix missing B100 core_compile (poor Git hygeine) | Nick Foster | 2012-01-23 | 1 | -0/+1 |
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| | | * | b100: bumped fpga compat number for slave fifo mode | Josh Blum | 2012-01-12 | 1 | -1/+1 |
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| | | * | Slave FIFO: fix for PKTEND not asserting @ end of RX. | Nick Foster | 2012-01-12 | 1 | -8/+8 |
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| | | * | B100: moar buffering on TX for better performance in bidirectional applications | Nick Foster | 2012-01-12 | 2 | -5/+5 |
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| | | * | Squashed slave mode changes onto master. | Nick Foster | 2012-01-12 | 7 | -34/+507 |
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| | * | | dsp rework: paramaterize post_engine_buffering | Josh Blum | 2012-02-01 | 3 | -4/+16 |
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| | * | | dsp_rework: handle longer headers | Matt Ettus | 2012-01-31 | 1 | -2/+8 |
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| | * | | dsp_rework: more thorough test | Matt Ettus | 2012-01-31 | 1 | -8/+20 |
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| | * | | dsp rework: finished engine HEADER_OFFSET stuff, add post_engine_buffering | Josh Blum | 2012-01-30 | 2 | -8/+13 |
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| | * | | dsp rework: work on 8 to 16 engine (usrp2 ok) | Josh Blum | 2012-01-30 | 2 | -25/+26 |
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| | * | | dsp_engine: work with transport header | Matt Ettus | 2012-01-30 | 1 | -16/+14 |
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| | * | | dsp rework: integrated dspengine_8to16, some tweaks | Josh Blum | 2012-01-30 | 3 | -8/+8 |
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| | * | | dsp: 8 to 16 bit conversion for tx side. believed to be functional | Matt Ettus | 2012-01-29 | 2 | -12/+230 |
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| | * | | dsp rework: increase the number of effective bits in the duc scale factor | Josh Blum | 2012-01-28 | 1 | -1/+1 |
| | | | | | | | | | | | | | | | | This will be useful for effecting the dynamic range of the sc8 tx mode. | ||||
| | * | | dsp rework: added double buffer interface to vita tx | Josh Blum | 2012-01-28 | 5 | -12/+41 |
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| | * | | dsp rework: moved scale and round into ddc chain | Josh Blum | 2012-01-28 | 7 | -41/+49 |
| | | | | | | | | | | | | | | | | 16to8 engine now performs only a clip from 16->8 | ||||
| | * | | dsp rework: top level fixes B100/E100 | Josh Blum | 2012-01-27 | 4 | -8/+9 |
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| | * | | dsp rework: integrated custom dsp module shells | Josh Blum | 2012-01-27 | 18 | -38/+370 |
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