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| * | reorder the memory mapMatt Ettus2009-12-112-2/+2
| * | put new setting reg into the address space in the right placeMatt Ettus2009-12-111-1/+1
| * | only pull from input fifo when really consuming or pushing into the next fifoMatt Ettus2009-12-111-1/+1
| * | Add ability to clear state out when there is an underrunMatt Ettus2009-12-111-1/+6
| * | fixed typo in u2_core.v resulting in unconnected net. added debug pinsMatt Ettus2009-12-113-14/+35
| * | ignore save filesMatt Ettus2009-12-091-0/+1
| * | First cut at vita tx, whole thing compilesMatt Ettus2009-12-093-27/+37
| * | flag packets which arrive way too early so the device doesn't sit there forever.Matt Ettus2009-12-091-2/+4
| * | very basic packet sending worksMatt Ettus2009-12-092-140/+50
| * | seems to correctly deframe packets. now need to consume them.Matt Ettus2009-12-081-12/+23
| * | progress on vita_tx. it compiles now, need to work on vita_tx_control.Matt Ettus2009-12-083-239/+182
| * | make the testbench work in this environment, without the crossclock settings busMatt Ettus2009-12-083-5/+8
| * | be a little more PC about itMatt Ettus2009-11-181-5/+9
| * | mostly just copied over from the rx side. Still needs a lot of work.Matt Ettus2009-11-183-13/+221
| * | forgot to declare wiresMatt Ettus2009-11-061-0/+4
| * | moved regs around for vita49Matt Ettus2009-11-052-12/+13
| * | vita rx instead of rx_control. Ready for firmware testing. Misses timing by...Matt Ettus2009-11-054-4/+48
| * | put 64 bit timer for vita49 on the settings busMatt Ettus2009-11-053-8/+17
| * | VITA49 rx (and tx skeleton) copied over from quad radioMatt Ettus2009-11-057-0/+1026
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| * This branch is for porting from the quad radio, and minor text cleanupsMatt Ettus2009-11-044-15/+259
| * earliest beta files renamed to avoid confusionMatt Ettus2009-10-116-0/+0
| * Properly reset the fifos. We didn't connect before.Matt Ettus2009-10-051-5/+5
| * Merge branch 'new_eth' of http://gnuradio.org/git/matt into masterJohnathan Corgan2009-10-01613-90023/+2518
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| | * Fix warnings, mostly from implicitly defined wires or unspecified widthsMatt Ettus2009-10-016-8/+14
| | * fullchip sim now compiles again, after moving eth and models over to new simp...Matt Ettus2009-10-015-17/+159
| | * remove unused opencoresMatt Ettus2009-10-01463-71885/+0
| | * Merge branch 'new_wb_intercon' into new_ethMatt Ettus2009-09-302-224/+239
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| | | * Copied wb_1master back from quad radioMatt Ettus2009-09-302-223/+238
| | * | no idea where this came from, it shouldn't be hereMatt Ettus2009-09-301-1/+1
| | * | Merge commit 'origin' into new_ethMatt Ettus2009-09-243-11/+24
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| | * | Merge branch 'serdes_newfifo' into new_ethMatt Ettus2009-09-203-79/+30
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| | | * | Untested fixes for getting serdes onto the new fifo system. Compiles, at leastMatt Ettus2009-09-043-79/+30
| | * | | Remove old mac. Good riddance.Matt Ettus2009-09-1064-15211/+0
| | * | | remove unused portMatt Ettus2009-09-101-1/+1
| | * | | More xilinx fifos, more clean up of our fifosMatt Ettus2009-09-1012-129/+555
| | * | | might as well use a cascade fifo to help timing and give a little more capacityMatt Ettus2009-09-101-1/+1
| | * | | fix a typo which caused tx glitchesMatt Ettus2009-09-051-1/+1
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| | * | Implement Eth flow control using pause framesMatt Ettus2009-09-045-73/+66
| | * | parameterized fifo sizes, some reformattingMatt Ettus2009-09-042-54/+57
| | * | remove unused old style fifoMatt Ettus2009-09-041-31/+0
| | * | allow control of whether or not to honor flow control, adds some debug linesMatt Ettus2009-09-041-6/+16
| | * | debug the rx sideMatt Ettus2009-09-041-1/+6
| | * | no longer used, replaced by newfifo versionMatt Ettus2009-09-041-66/+0
| | * | seems to build a decent fpga, but still some issues with a full connection.Matt Ettus2009-09-033-29/+36
| | * | MAC transmit seems to work now. The root cause of the problem was accidental...Matt Ettus2009-09-034-67/+70
| | * | set device to xc3s2000. Shouldn't make any differences.Matt Ettus2009-09-031-2/+2
| | * | misc ignoresMatt Ettus2009-09-032-0/+3
| | * | made a new block ram based fifo, 64 (65) elements long, all fifos now have "e...Matt Ettus2009-09-0328-155/+652
| | * | bring the testbench files up to dateMatt Ettus2009-09-024-88/+79
| | * | major cleanup of 2 clock fifosMatt Ettus2009-09-024-29/+48
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