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The counter is for performance monitoring in firmware, priority encoder
and new interrupt controller are from quad radio and speed up interrupts.
This is tested and it works for me.
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* 'new_eth' of http://gnuradio.org/git/matt: (42 commits)
Fix warnings, mostly from implicitly defined wires or unspecified widths
fullchip sim now compiles again, after moving eth and models over to new simple_gemac
remove unused opencores
remove debugging code
no idea where this came from, it shouldn't be here
Copied wb_1master back from quad radio
Remove old mac. Good riddance.
remove unused port
More xilinx fifos, more clean up of our fifos
might as well use a cascade fifo to help timing and give a little more capacity
fix a typo which caused tx glitches
Untested fixes for getting serdes onto the new fifo system. Compiles, at least
Implement Eth flow control using pause frames
parameterized fifo sizes, some reformatting
remove unused old style fifo
allow control of whether or not to honor flow control, adds some debug lines
debug the rx side
no longer used, replaced by newfifo version
remove special last_line adjustment from ethernet port
Firmware now inserts mac source address value in each frame.
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simple_gemac
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Functionality should not change at all
Conflicts:
usrp2/fpga/top/u2_core/u2_core.v
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more sane config options, should be exactly the same memory map
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Conflicts:
.gitignore
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Not fully tested, but it seems to work without frame errors, sequence
number errors or ethernet overruns. Still of course will get tx underruns
on a slow machine, and the transmitted signal has some issues though.
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accidentally using the rx_clk in one stage of the fifos on the tx side.
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"enhanced level logic" for accurate fullness. Maybe this will help...
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and fifo_2clock.v are empty
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missing. MDIO seems ok.
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* svn diff http://gnuradio.org/svn/branches/developers/matt/new_eth
-r10782:11633
* Patch applied with no conflicts or fuzz.
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"run" signal. This is important for MIMO. Bug reported by Christoph Hein and Hanwen .
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This is a custom build for USRP2 FPGA. It allows using a BasicRX or
LFRX board and feed two independent, real signals. In addition, instead
of the CIC/HB decimator, which optimizes frequency response, it uses an
integrate and dump decimator, which optimizes for time-domain impulse
response.
These changes have been made in dsp_core_rx.v:
* A second DDC has been added, sharing a frequency register with
the existing DDC.
* The output of the two DDCs are interleaved as I1 Q1 I2 Q2I ...
into the receive FIFO. This limits the host configured decimation
to 8 intead of 4. Use gr.deinterleave to recover the streams.
* The ADCs are hardcoded:
RX_A ==> DDC #1 I-input
0 ==> DDC #1 Q-input
RX_B ==> DDC #2 I-input
0 ==> DDC #2 Q-input
Thus, the input mux has been disabled.
* The CIC/HB decimator has been replaced by an integrate and dump at
the decimation rate.
* To assist with meeting timing, the external RAM has been disabled.
The basic application is to coherently sample two real IF streams and
downconvert to baseband, while minimizing the impulse response duration
of the resampling filters.
git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@11519 221aa14e-8319-0410-a670-987f0aec2ac5
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git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@10926 221aa14e-8319-0410-a670-987f0aec2ac5
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FPGA build to use integrate-and-dump decimator instead of CIC/HB combination. This provides a much shorter time duration impulse response for the same decimation rate, at the expense of worse stop-band rejection.
git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@10888 221aa14e-8319-0410-a670-987f0aec2ac5
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git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@10814 221aa14e-8319-0410-a670-987f0aec2ac5
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git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@10813 221aa14e-8319-0410-a670-987f0aec2ac5
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git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@10779 221aa14e-8319-0410-a670-987f0aec2ac5
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git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@10769 221aa14e-8319-0410-a670-987f0aec2ac5
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