Commit message (Collapse) | Author | Age | Files | Lines | |
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* | b100: tighten timing, added p2p constraint + ignores | Josh Blum | 2013-03-05 | 2 | -2/+7 |
| | | | | Bumped u1p compat minor, now its 11.2 | ||||
* | b100: install rx data minimum occupancy logic | Josh Blum | 2012-10-09 | 1 | -3/+5 |
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* | b100: added final fifo for min occupancy check | Josh Blum | 2012-10-09 | 1 | -5/+22 |
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* | b100: fix syntax error in packet_padder36 | Josh Blum | 2012-10-09 | 1 | -1/+1 |
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* | b100/e100: bump compat for inversion fix on master | Josh Blum | 2012-10-05 | 1 | -1/+1 |
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* | e1x0: fix RX ADC I and Q inversion | Josh Blum | 2012-10-05 | 1 | -1/+10 |
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* | Merge branch 'maint' | Josh Blum | 2012-10-05 | 1 | -4/+4 |
|\ | | | | | | | | | | | | | Conflicts: usrp2/top/B100/u1plus_core.v usrp2/top/E1x0/E1x0.v usrp2/top/E1x0/u1e_core.v | ||||
| * | b100/e100: bump compat minor for inversion fix | Josh Blum | 2012-10-05 | 2 | -2/+2 |
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| * | e1x0: fix RX ADC I and Q inversion | Josh Blum | 2012-10-05 | 1 | -2/+13 |
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| * | b100: fix RX ADC I and Q inversion | Josh Blum | 2012-10-05 | 1 | -4/+4 |
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* | | b100: fpga makefile for 2rx no tx | Josh Blum | 2012-09-01 | 4 | -1/+134 |
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* | | e100: tighten timing - less routing on EM_A | Josh Blum | 2012-07-19 | 4 | -4/+4 |
| | | | | | | | | | | There were a few places it was ok to use addr over EM_A. This makes routing sligtly easier for GPMC signals. | ||||
* | | u1plus: added sr misc hook for clock sync | Josh Blum | 2012-07-18 | 1 | -1/+8 |
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* | | e100: renamed top level for E100/E110 to E1x0 | Josh Blum | 2012-07-17 | 6 | -16/+16 |
| | | | | | | | | Some minor tweaks to gpmc_to_fifo + timing | ||||
* | | E100: squash E100/E110 top level work | Josh Blum | 2012-07-16 | 6 | -531/+84 |
| | | | | | | | | | | | | Implements timed commands and FIFO control. Uses control and data FIFOs for GPMC. Uses the common core for E100/B100. | ||||
* | | gpmc: squashed GPMC FIFO work for E100 | Josh Blum | 2012-07-16 | 5 | -162/+93 |
| | | | | | | | | | | The control and data slaves are now both implemented as FIFOs. Requires another squash of E100 top level to use. | ||||
* | | gpmc: tighter timing constraints and easier to route gpmc to fifo | Josh Blum | 2012-07-16 | 2 | -26/+37 |
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* | | Merge branch 'master' into next | Josh Blum | 2012-07-16 | 3 | -43/+6 |
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| * | | Merge branch 'maint' | Josh Blum | 2012-07-16 | 3 | -43/+6 |
| |\| | | | | | | | | | | | | | Conflicts: usrp2/top/E1x0/u1e_core.v | ||||
| | * | e100: offset gpmc to fifo writes by 2 transfers | Josh Blum | 2012-07-15 | 2 | -5/+5 |
| | | | | | | | | | | | | This effectivly works around bus initial transaction issues. | ||||
| | * | e100: reverted commit registering in gpmc | Josh Blum | 2012-07-15 | 1 | -38/+1 |
| | | | | | | | | | | | | There is a subtle bus issue that the last changset did not address. | ||||
* | | | B100: squash B100 top level work | Josh Blum | 2012-07-02 | 4 | -406/+348 |
| | | | | | | | | | | | | | | | | | | Implements timed commands and FIFO control. Uses control and data FIFOs for GPIF. Implements a common core for E100/B100. | ||||
* | | | gpif: squashed GPIF slave fifo work for B100 | Josh Blum | 2012-07-02 | 4 | -414/+319 |
| | | | | | | | | | | | | | | | The control and data enpoints are now both implemented as FIFOs. Requires another squash of B100 top level to use. | ||||
* | | | fifo: added module packet_padder36 to fifo/ | Josh Blum | 2012-07-02 | 2 | -1/+157 |
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* | | b100: removed unused proto files | Josh Blum | 2012-06-13 | 3 | -390/+0 |
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* | | fpga: added setting regs based simple_i2c_core | Josh Blum | 2012-05-30 | 2 | -0/+117 |
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* | | fpga: added some parameterization to settings_fifo_ctrl | Josh Blum | 2012-05-30 | 1 | -3/+6 |
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* | | fpga: added various models from ISE | Josh Blum | 2012-05-30 | 7 | -0/+4011 |
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* | | Merge branch 'maint' | Josh Blum | 2012-05-22 | 1 | -1/+38 |
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| * | Added registers for gpmc-to-fifo interface to address sequence errors for ↵ | Al Fayez | 2012-05-22 | 1 | -1/+38 |
| | | | | | | | | E100/E110 | ||||
* | | Merge branch 'maint' | Josh Blum | 2012-05-10 | 2 | -7/+9 |
|\| | | | | | | | | | Conflicts: usrp2/top/E1x0/u1e_core.v | ||||
| * | e100: bump compat minor for xclock reader fix | Josh Blum | 2012-05-10 | 1 | -1/+1 |
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| * | fpga: xclock fix for edge case condition | Josh Blum | 2012-05-08 | 1 | -6/+8 |
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* | | e100/b100: bumped compat number for timed commands merge | Josh Blum | 2012-04-25 | 2 | -2/+2 |
| | | | | | | | | | | There were common FPGA changes and an incompatibility. This should have been done before the merge anyhow. | ||||
* | | slave_fifo: use 2KB FIFO size instead of 1KB | Nick Foster | 2012-04-24 | 1 | -1/+1 |
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* | | b100: implement packet-end/flush cycle timeout | Josh Blum | 2012-04-24 | 3 | -12/+26 |
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* | | gpif: removed unused gpif related files | Josh Blum | 2012-04-24 | 8 | -908/+1 |
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* | | N2x0: updated the bootloader w/ latest from fw | Josh Blum | 2012-04-20 | 1 | -390/+390 |
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* | | usrp2: remove settings_fifo_ctrl, meets timing | Josh Blum | 2012-04-20 | 1 | -2/+11 |
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* | | fifo ctrl: Nseries timing meets with a single shortfifo | Josh Blum | 2012-04-17 | 1 | -3/+2 |
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* | | usrp: work on meeting timing constraints | Josh Blum | 2012-04-10 | 5 | -25/+30 |
| | | | | | | | | | | | | * fifo ctrl register the vita ticks and use late * vita de/framer make nchans const since we dont change it * simplify readback muxes to minimal usage | ||||
* | | Merge branch 'master' into next | Josh Blum | 2012-04-09 | 5 | -7/+67 |
|\ \ | | | | | | | | | | | | | | | | Conflicts: usrp2/top/N2x0/u2plus_core.v usrp2/top/USRP2/u2_core.v | ||||
| * | | Merge branch 'maint' | Josh Blum | 2012-04-09 | 5 | -6/+6 |
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| | * | vita: moved clear register to overlap with nchan register | Josh Blum | 2012-04-09 | 5 | -6/+6 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This fixes the bug where setting the format clears the vita RX. This is only an issue when the noclear option is set by UHD, because the format register is always so, so it always clears. Note: noclear is there to support the backwards compat API (pre streamer). Now, numchans and clear overlap. This is ok because in the host code, clear and numchans are always used together. All timing meets on N2xx and USRP2. | ||||
| * | | Merge branch 'maint' | Josh Blum | 2012-04-02 | 2 | -5/+5 |
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| | * | b100: fix slave fifo data xfer exit condition | Josh Blum | 2012-04-01 | 2 | -5/+5 |
| | | | | | | | | | | | | | | | | | | | | | When exiting the read/write data state, when the transfer count maxes out/peaks, the fifo read/write signals were getting this condition the cycle after with the state change. | ||||
| * | | fpga: extract usage summary from map file | Josh Blum | 2012-03-27 | 1 | -0/+60 |
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* | | Merge branch 'master' into next | Josh Blum | 2012-03-26 | 4 | -85/+92 |
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| * | B100: port cleanups from b100-txbug to this branch | Nick Foster | 2012-03-26 | 2 | -28/+21 |
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| * | fpga: fifo_2clock handles widths and sizes in-between corgens | Josh Blum | 2012-03-25 | 1 | -21/+23 |
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