| Commit message (Expand) | Author | Age | Files | Lines |
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| * | Merge branch 'master' into next | Josh Blum | 2012-04-09 | 5 | -7/+67 |
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| | * | Merge branch 'maint' | Josh Blum | 2012-04-09 | 5 | -6/+6 |
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| | | * | vita: moved clear register to overlap with nchan register | Josh Blum | 2012-04-09 | 5 | -6/+6 |
| | * | | Merge branch 'maint' | Josh Blum | 2012-04-02 | 2 | -5/+5 |
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| | | * | b100: fix slave fifo data xfer exit condition | Josh Blum | 2012-04-01 | 2 | -5/+5 |
| | * | | fpga: extract usage summary from map file | Josh Blum | 2012-03-27 | 1 | -0/+60 |
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| * | | Merge branch 'master' into next | Josh Blum | 2012-03-26 | 4 | -85/+92 |
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| | * | B100: port cleanups from b100-txbug to this branch | Nick Foster | 2012-03-26 | 2 | -28/+21 |
| | * | fpga: fifo_2clock handles widths and sizes in-between corgens | Josh Blum | 2012-03-25 | 1 | -21/+23 |
| | * | b100: cleanup redundant logic for slwr and slrd | Josh Blum | 2012-03-25 | 1 | -2/+2 |
| | * | b100: extra data pktend cycle for fifo addr | Josh Blum | 2012-03-25 | 1 | -2/+8 |
| | * | b100: slave fifo fix for dst/src ready signals | Josh Blum | 2012-03-24 | 2 | -35/+41 |
| * | | spi core: ready logic low one cycle earlier | Josh Blum | 2012-03-16 | 1 | -1/+1 |
| * | | fifo ctrl: parameterize having a proto header | Josh Blum | 2012-03-16 | 4 | -10/+12 |
| * | | fifo ctrl: rename fifo ctrl module and add sid ack param | Josh Blum | 2012-03-16 | 4 | -37/+40 |
| * | | fifo ctrl: minor fixes for spi core, swap time define | Josh Blum | 2012-03-16 | 5 | -10/+10 |
| * | | fifo ctrl: simplified perfs, added spi clock idle phase | Josh Blum | 2012-03-16 | 5 | -333/+341 |
| * | | fifo ctrl: minor fixes from last commit | Josh Blum | 2012-03-16 | 3 | -366/+366 |
| * | | fifo ctrl: spi core work, fifo ctrl perifs, usrp2 support | Josh Blum | 2012-03-16 | 5 | -370/+429 |
| * | | spi: created simple spi core (sr based) | Josh Blum | 2012-03-16 | 4 | -383/+593 |
| * | | fifo ctrl: simplified result packets (no tsf or sid) | Josh Blum | 2012-03-16 | 1 | -16/+7 |
| * | | fifo_ctrl: switched to medfifo and separate result fifo | Josh Blum | 2012-03-16 | 3 | -92/+122 |
| * | | fifo_ctrl: clear settings reg, and flow control | Josh Blum | 2012-03-16 | 3 | -10/+17 |
| * | | fifo ctrl: added time compare for timed commands | Josh Blum | 2012-03-16 | 1 | -3/+7 |
| * | | srb: created command queue, in and out state machines | Josh Blum | 2012-03-16 | 3 | -99/+162 |
| * | | usrp2: added vrt pack/unpacker to fifo ctrl | Josh Blum | 2012-03-16 | 1 | -40/+107 |
| * | | usrp2: first pass implementation of fifo control | Josh Blum | 2012-03-16 | 6 | -10/+594 |
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| * | fpga: force -include_global for custom sources | Josh Blum | 2012-03-12 | 9 | -13/+16 |
| * | fpga: fix custom defs in some top level makefiles | Josh Blum | 2012-03-08 | 4 | -101/+3 |
| * | usrp2/nseries: added churn to meet timing | Josh Blum | 2012-02-18 | 2 | -2/+4 |
| * | vita rx: trigger clear after packet tranfer | Josh Blum | 2012-02-18 | 1 | -2/+22 |
| * | dsp rework: fix dspengine_8to16 to handle padded packets | Josh Blum | 2012-02-17 | 1 | -4/+3 |
| * | dsp_engine: fix for upper/lower swap, and odd length packets | Matt Ettus | 2012-02-16 | 1 | -16/+20 |
| * | dsp rework: added flusher to vita tx chain on clear | Josh Blum | 2012-02-15 | 1 | -8/+16 |
| * | dsp rework: minor simplification in vita_tx_deframer | Josh Blum | 2012-02-13 | 1 | -4/+1 |
| * | dsp rework: full-rate pipelining in vita tx deframer | Josh Blum | 2012-02-12 | 1 | -37/+51 |
| * | dsp rework: pass enables into glue, update power trig, parameterize, fix modu... | Josh Blum | 2012-02-10 | 9 | -103/+145 |
| * | dsp rework: implement 64 bit ticks no seconds | Josh Blum | 2012-02-06 | 10 | -111/+57 |
| * | B100: External FPGA reset from FX2 reuses fpga_cfg_cclk. | Nick Foster | 2012-02-06 | 2 | -2/+6 |
| * | dsp rework: pass vita clears into dsp modules, unified fifo clears | Josh Blum | 2012-02-04 | 14 | -81/+76 |
| * | b100: timing constraints on GPIF lines | Josh Blum | 2012-02-04 | 1 | -0/+9 |
| * | b100: connect all clears for gpif | Josh Blum | 2012-02-03 | 3 | -15/+8 |
| * | power_trig: test code for power trigger | Matt Ettus | 2012-02-02 | 1 | -0/+71 |
| * | dsp rework: rehash of the custom module stuff and readme | Josh Blum | 2012-02-02 | 26 | -262/+544 |
| * | power_trig: first cut at power trigger with fixed delay | Matt Ettus | 2012-02-02 | 2 | -2/+115 |
| * | dsp_rework: testbench enhancements | Matt Ettus | 2012-02-02 | 1 | -11/+34 |
| * | dsp rework: custom engine module for rx/tx vita chain | Josh Blum | 2012-02-01 | 13 | -138/+294 |
| * | dsp rework: register the sample in vita tx ctrl | Josh Blum | 2012-02-01 | 1 | -2/+11 |
| * | Merge branch 'slave_fifo_rebase' into dsp_rework | Josh Blum | 2012-02-01 | 6 | -35/+509 |
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| | * | Fix missing B100 core_compile (poor Git hygeine) | Nick Foster | 2012-01-23 | 1 | -0/+1 |
